本文選題：功率VDMOS器件　切入點(diǎn)：緊湊模型　出處：《東南大學(xué)》2015年碩士論文

【摘要】：垂直雙擴(kuò)散金屬-氧化物半導(dǎo)體場(chǎng)效應(yīng)晶體管(VDMOS)由于高輸入阻抗、低驅(qū)動(dòng)功率及高開(kāi)關(guān)速度等優(yōu)勢(shì),已廣泛應(yīng)用于各種功率集成電路領(lǐng)域。SPICE器件模型是由SPICE仿真器使用的基于文本描述的模型,是連接器件工藝與電路設(shè)計(jì)的橋梁。然而,目前業(yè)界還沒(méi)有被廣泛認(rèn)可的功率VDMOS器件SPICE模型,為此,針對(duì)功率VDMOS器件SPICE模型的深入研究意義重大。本文系統(tǒng)建立了一套完整的功率VDMOS器件SPICE模型,包括基于表面勢(shì)的直流特性模型和基于電荷的交流特性模型。直流特性建模時(shí),將器件分為溝道區(qū)、積累層電阻區(qū)、寄生JFET區(qū)、N-外延層區(qū)以及N+襯底區(qū)5個(gè)部分,提出了全新的基于表面勢(shì)的溝道區(qū)模型和積累層電阻模型,進(jìn)而對(duì)寄生JFET區(qū)耗盡及夾斷兩種狀態(tài)進(jìn)行分析,建立了寄生JFET區(qū)模型,根據(jù)外延層區(qū)和襯底區(qū)的電流路徑,建立了N-外延層模型和N+襯底區(qū)模型。另外,本文還建立了包括柵源電容Cgs模型、柵漏電容Cgd模型、漏源電容Cds模型在內(nèi)的交流特性模型。隨后,通過(guò)Verilog-A語(yǔ)言對(duì)上述功率VDMOS器件模型進(jìn)行描述,運(yùn)用測(cè)試平臺(tái)獲取器件的直流特性數(shù)和交流特性數(shù)據(jù)。最后,根據(jù)上述的器件模型和測(cè)試數(shù)據(jù),進(jìn)行模型參數(shù)提取工作,并給出基于模型仿真數(shù)據(jù)的驗(yàn)證結(jié)果。本文建立的功率VDMOS器件SPCIE模型具有明確的物理意義,模型仿真速度快、收斂性高；驗(yàn)證結(jié)果表明,直流特性模型的仿真曲線與測(cè)試數(shù)據(jù)之間的均方根誤差均在5%以?xún)?nèi),交流特性模型均在7%以?xún)?nèi),并能直接應(yīng)用于SPICE仿真軟件,實(shí)現(xiàn)了論文的預(yù)期目標(biāo)。
[Abstract]:Vertical double diffusion metal-oxide semiconductor field effect transistor (VDMOS) has the advantages of high input impedance, low driving power and high switching speed. Spice device model is a text-based model used by SPICE simulator and is a bridge between connector process and circuit design. At present, there is no widely recognized SPICE model for power VDMOS devices. Therefore, it is of great significance to study the SPICE model of power VDMOS devices. In this paper, a complete SPICE model of power VDMOS devices is established. It includes DC characteristic model based on surface potential and AC characteristic model based on charge. In DC characteristic modeling, the device is divided into five parts: channel region, accumulative layer resistance region, parasitic JFET region, N-epitaxial layer region and N substrate region. A new channel region model based on surface potential and an accumulative layer resistance model are proposed. The parasitic JFET region depletion and clamping states are analyzed, and the parasitic JFET region model is established according to the current paths in the epitaxial layer and substrate region. N- epitaxial layer model and N substrate model are established. In addition, the AC characteristic models including gate source capacitance Cgs model, gate leakage capacitance Cgd model, drain source capacitance Cds model are also established. The model of the power VDMOS device is described by Verilog-A language, and the DC characteristic number and AC characteristic data of the device are obtained by using the test platform. Finally, according to the above device model and test data, the model parameters are extracted. The power VDMOS device SPCIE model established in this paper has clear physical significance, fast simulation speed and high convergence. The root mean square error between the DC characteristic model and the test data is less than 5%, and the AC characteristic model is less than 7%. It can be directly applied to the SPICE simulation software and achieve the expected goal of the paper.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN386

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