本文選題：物理設(shè)計(jì)　切入點(diǎn)：低功耗　出處：《湘潭大學(xué)》2015年碩士論文

【摘要】：本文針對(duì)一款物聯(lián)網(wǎng)控制的DSP芯片ADP32,在后端物理設(shè)計(jì)中提出了一種優(yōu)化的時(shí)鐘樹綜合方法。實(shí)驗(yàn)數(shù)據(jù)表明該方法在確保電路時(shí)序收斂的前提下有效精簡了時(shí)鐘樹結(jié)構(gòu),減小了時(shí)鐘樹功耗和面積,目前該款芯片已經(jīng)成功進(jìn)入流片階段。時(shí)鐘信號(hào)是電路正常工作的基準(zhǔn),也是電路系統(tǒng)中連線最長、翻轉(zhuǎn)率最高、負(fù)載最大的信號(hào)。時(shí)鐘信號(hào)必須保證芯片處于最差環(huán)境時(shí),最關(guān)鍵的時(shí)序也能夠正常工作,否則就會(huì)導(dǎo)致時(shí)序紊亂,電路功能出錯(cuò)。ASIC后端物理設(shè)計(jì)中的時(shí)鐘樹綜合優(yōu)化是將前端綜合時(shí)的理想時(shí)鐘信號(hào)換成實(shí)際信號(hào)連線,也是整個(gè)后端設(shè)計(jì)中十分關(guān)鍵的一步。時(shí)鐘樹綜合的目的是最小化時(shí)鐘延時(shí)和偏差,最大限度的獲得時(shí)序收斂,同時(shí)精簡時(shí)鐘緩沖器數(shù)目和最小化面積,降低時(shí)鐘樹功耗�？傊�,一個(gè)時(shí)鐘樹的好壞直接影響整個(gè)芯片的面積、功耗和布通率。本文是基于Cadence公司的布局布線工具SOC Encounter平臺(tái),結(jié)合ADP32芯片的后端物理設(shè)計(jì)流程,展開的時(shí)鐘樹綜合優(yōu)化研究。首先簡單介紹了后端設(shè)計(jì)的基本流程和各個(gè)流程階段的內(nèi)容及注意事項(xiàng);然后針對(duì)本論文的研究課題時(shí)鐘樹綜合優(yōu)化詳細(xì)闡述涉及到的基本原理和時(shí)鐘網(wǎng)絡(luò)分類;最后通過仔細(xì)分析本設(shè)計(jì)的時(shí)鐘樹結(jié)構(gòu),結(jié)合在實(shí)際項(xiàng)目中遇到的問題進(jìn)行分析并提出解決方案,另外在確保時(shí)序收斂的前提下,提出一種通過優(yōu)化和設(shè)置時(shí)鐘樹指導(dǎo)文件中的Buffer、Global Excluded Pin及Leaf Pin Group三個(gè)參數(shù)綜合得到功耗低、面積小時(shí)鐘樹的方法。實(shí)驗(yàn)結(jié)果表明,這三種參數(shù)的合理利用,相比于傳統(tǒng)時(shí)鐘樹綜合方法,時(shí)鐘樹功耗優(yōu)化了3.6%,芯片面積減小了0.4%。
[Abstract]:In this paper, an optimized clock tree synthesis method is proposed for ADP32, a DSP chip controlled by the Internet of things. Experimental data show that the proposed method can effectively simplify the clock tree structure while ensuring the convergence of circuit timing. It has reduced the power consumption and area of the clock tree. At present, the chip has successfully entered the stage of the stream chip. The clock signal is the reference for the circuit to work normally, and it is also the longest connection and the highest turnover rate in the circuit system. The most loaded signal. The clock signal must ensure that the chip is in the worst environment, the most critical timing can also work properly, otherwise it will lead to timing disorder, The optimization of clock tree synthesis in the backend physical design of ASIC is to replace the ideal clock signal with the actual signal line. The purpose of clock tree synthesis is to minimize clock delay and deviation, maximize timing convergence, and reduce the number of clock buffers and minimize the area. In a word, the quality of a clock tree directly affects the area, power consumption and routing rate of the whole chip. This paper is based on the layout and wiring tool SOC Encounter platform of Cadence Company, combined with the back-end physical design flow of ADP32 chip. Firstly, the basic flow of the back-end design, the contents of each process and the points for attention are introduced. Then, the basic principle and the classification of clock network are elaborated in detail for the research topic of this thesis. Finally, the clock tree structure of this design is analyzed carefully. Combined with the problems encountered in the actual project to analyze and propose solutions, in addition to ensure the convergence of time series, A method of synthesizing the three parameters of buffer Global Excluded Pin and Leaf Pin Group in the clock-tree guidance file to obtain low power consumption and small area clock tree is proposed. The experimental results show that the three parameters are reasonably utilized. Compared with the traditional clock tree synthesis method, the clock tree power consumption is optimized by 3.6 and the chip area is reduced by 0.4.
【學(xué)位授予單位】：湘潭大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN402

【參考文獻(xiàn)】

相關(guān)碩士學(xué)位論文 前1條

1 于雪紅;互連線統(tǒng)計(jì)時(shí)序的符號(hào)化分析方法[D];上海交通大學(xué);2009年

，

本文編號(hào)：1667715