本文選題：故障注入　切入點：現(xiàn)場可編程邏輯門陣列　出處：《哈爾濱工業(yè)大學(xué)》2015年碩士論文

【摘要】：近年來,FPGA呈現(xiàn)出迅猛發(fā)展的態(tài)勢,廣泛應(yīng)用于航天、航空、金融等國防、民生領(lǐng)域。然而由于自身構(gòu)造的原因,使其極容易在各種復(fù)雜的環(huán)境中發(fā)生故障,因此這些領(lǐng)域的專用計算機都會配有相應(yīng)的容錯系統(tǒng)。而為了驗證這些系統(tǒng)的可靠性與容錯性,則需要專門的故障注入工具進行精確而實時的在線注入。這便是本文研究的重點。本文針對當(dāng)前主流的SRAM型FPGA進行了簡單的分析,指出了其容易發(fā)生的單粒子翻轉(zhuǎn)軟錯誤與單粒子閂鎖的硬錯誤。將FPGA系統(tǒng)劃分為已知源碼的白盒目標(biāo)系統(tǒng)與未知源碼的黑盒目標(biāo)系統(tǒng)。針對前者,通過分析當(dāng)前主流的代碼修改技術(shù),決定采用支持突變技術(shù)的分支語句修改策略,借助硬件描述語言,將故障從門級傳播到I/O管腳。針對黑盒目標(biāo)系統(tǒng),先簡要分析了傳統(tǒng)硬件及各種總線故障注入的優(yōu)缺點,然后針對1553B總線,介紹了其總線的特性,并基于這些特性提出了接口模擬的故障注入方案,主要包括硬件接口與協(xié)議接口,利用FPGA在總線傳播過程中引入故障。本文依據(jù)這兩種技術(shù),均開發(fā)了一套故障注入工具。支持注入固定0、固定1、翻轉(zhuǎn)等故障類型。在FPGA內(nèi)部,支持最多16個信號的故障疊加與觸發(fā);在1553B總線傳播過程中,支持注入位置包括同步頭、奇偶校驗位、數(shù)據(jù)位,并可同時對數(shù)據(jù)字、命令字、狀態(tài)字進行注入。最后本文使用設(shè)計的故障注入工具,驗證了控制系統(tǒng)與總線的容錯性能,成功注入了故障。得出結(jié)論:針對不同的FPGA系統(tǒng),無論是在系統(tǒng)內(nèi)部添加注入單元還是在模擬接口處修改信號,均可實現(xiàn)故障的注入。
[Abstract]:In recent years, FPGA has shown a rapid development, widely used in aerospace, aviation, finance and other areas of national defense, people's livelihood. However, due to the reasons of its own structure, it is easy to fail in various complex environments. Therefore, specialized computers in these fields will be equipped with corresponding fault-tolerant systems. In order to verify the reliability and fault-tolerance of these systems, This is the focus of this paper. This paper makes a simple analysis of the current mainstream SRAM type FPGA. The paper points out that the soft error of single particle flip and the hard error of single particle latch occur easily. The FPGA system is divided into the known source code white box target system and the unknown source black box target system. By analyzing the current mainstream code modification techniques, we decide to adopt the branch statement modification strategy which supports the mutation technique, and with the help of hardware description language, we can spread the fault from the gate level to the I / O pin, aiming at the black box target system. In this paper, the advantages and disadvantages of traditional hardware and various bus fault injection are analyzed briefly, then the characteristics of 1553B bus are introduced, and based on these characteristics, a fault injection scheme of interface simulation is proposed. It mainly includes hardware interface and protocol interface, using FPGA to introduce fault in the process of bus propagation. According to these two technologies, a set of fault injection tools are developed in this paper, which support injection fixed 0, fixed 1, flip and other fault types. During the 1553B bus propagation, the injection position includes synchronous head, parity check bit, data bit, and can be simultaneously used for data word and command word. Finally, the fault tolerant performance of the control system and the bus is verified by using the designed fault injection tool, and the fault is successfully injected. The conclusion is as follows: for different FPGA systems, The fault injection can be realized either by adding the injection unit inside the system or modifying the signal at the analog interface.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN791

【參考文獻】

相關(guān)期刊論文 前1條

1 王建瑩,孫峻朝,楊孝宗;容錯計算機系統(tǒng)可靠性評估工具:HFI-2故障注入器[J];電子學(xué)報;1999年11期

，

本文編號：1665119