本文選題：合成頻率源　切入點：多路信號輸出　出處：《電子科技大學(xué)》2017年碩士論文

【摘要】：為了滿足自動測試系統(tǒng)中對不同時鐘信號的需求,本課題對低噪聲頻率源關(guān)鍵技術(shù)進行了分析,并給出了一種低相位噪聲時鐘信號的產(chǎn)生方法。在此基礎(chǔ)上,設(shè)計了一個多路輸出的低噪聲合成頻率源,實現(xiàn)了多個高精度、低噪聲的時鐘信號輸出。本文首先針對低噪聲多路輸出合成頻率源的關(guān)鍵技術(shù)進行了分析,包括對各種頻率合成方式進行了對比,對鎖相式合成頻率源的原理及影響噪聲的環(huán)節(jié)進行了分析,對多路信號輸出模塊及合成頻率源的噪聲抑制方法進行了研究。然后通過對不同方案的原理進行仿真分析與對比,設(shè)計并實現(xiàn)了多路輸出的低噪聲合成頻率源。最后對設(shè)計調(diào)試過程中的關(guān)鍵難點進行了分析。本文主要內(nèi)容包括以下幾個方面:一、多路信號輸出的合成頻率源方案設(shè)計。頻率合成模塊是合成頻率源的核心部分。本文對多種頻率合成方式的特點進行分析和對比,結(jié)合實際需求,采用了多路獨立鎖相環(huán)電路加時鐘緩沖器的電路結(jié)構(gòu),實現(xiàn)了目標頻率的合成,并通過相互獨立的信號調(diào)理通道輸出,保證了輸出信號符合技術(shù)指標要求。二、鎖相環(huán)電路分析及其控制電路設(shè)計。對鎖相環(huán)電路特性進行了分析和仿真,研究了環(huán)路濾波器對相位噪聲和鎖定時間的影響。并給出了頻率控制字的寫入方法及控制電路。三、輸出信號的低噪聲設(shè)計。分析了影響輸出信號相位噪聲的各個環(huán)節(jié),具體包括信號的產(chǎn)生電路、信號的放大與濾波器電路、供電電源等。對影響輸出信號相位噪聲的主要電路進行低噪聲設(shè)計。四、實現(xiàn)了完整的硬件電路,并進行了調(diào)試及詳細測試。驗證了多路信號輸出的合成頻率源設(shè)計方案,總結(jié)了調(diào)試過程中遇到的問題和解決方法。經(jīng)過測試驗證,所有輸出信號頻率精度均在0.1ppm以內(nèi),輸出信號功率及相位噪聲指標均滿足要求。通過本課題給出的多路輸出方案,10MHz輸出信號精度達到了0.02ppm以內(nèi),輸出信號間的延遲達到100ps以內(nèi)。并通過輸出信號的降噪處理,輸出信號近旁單邊相噪有明顯優(yōu)化。
[Abstract]:In order to meet the requirements of different clock signals in automatic test system, the key technology of low noise frequency source is analyzed in this paper, and a method of producing low phase noise clock signal is given. In this paper, a low noise synthesizing frequency source with multiple outputs is designed, and several clock signals with high precision and low noise are realized. Firstly, the key technology of synthesizing frequency source with low noise output is analyzed in this paper. Including the comparison of various frequency synthesis methods, the principle of phase-locked synthesis frequency source and the influence of noise are analyzed. The noise suppression methods of multi-channel signal output module and synthetic frequency source are studied, and then the principle of different schemes is simulated and compared. A low noise synthesizing frequency source with multiple output is designed and implemented. Finally, the key difficulties in the design and debugging are analyzed. The main contents of this paper are as follows: 1. The design of synthetic frequency source with multi-channel signal output. Frequency synthesis module is the core part of synthetic frequency source. The circuit structure of multi-channel independent phase-locked loop circuit and clock buffer is adopted to realize the synthesis of target frequency, and the output signal of independent signal conditioning channel is ensured that the output signal meets the technical requirements. Phase locked loop circuit analysis and control circuit design. The circuit characteristics of phase locked loop are analyzed and simulated, the influence of loop filter on phase noise and locking time is studied, and the writing method and control circuit of frequency control word are given. The low noise design of output signal is analyzed, including the circuit of signal generation, the circuit of signal amplification and filter, which affect the phase noise of output signal. The main circuits which affect the phase noise of the output signal are designed with low noise. Fourthly, the complete hardware circuit is realized, and the debugging and detailed testing are carried out. The design scheme of the synthetic frequency source of the multi-channel signal output is verified. The problems and solutions in debugging are summarized. The frequency accuracy of all output signals is within 0.1ppm. The output signal power and phase noise index meet the requirements. The output signal accuracy of 10MHz is within 0.02ppm, the delay between output signals is within 100ps, and the noise reduction of output signal is achieved by the de-noising processing of output signal. The one-sided phase noise near the output signal is obviously optimized.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN74

【參考文獻】

相關(guān)期刊論文 前1條

1 鐘催林;肖化武;李軍紅;;采用PLL技術(shù)的合成頻率源設(shè)計[J];國外電子元器件;2006年05期

相關(guān)碩士學(xué)位論文 前4條

1 劉民偉;10MHz-12GHz超寬帶接收機的設(shè)計與實現(xiàn)[D];電子科技大學(xué);2013年

2 王征;60MHz～12GHz寬帶頻率源研究[D];電子科技大學(xué);2010年

3 段維倫;低相噪Ka波段射頻收發(fā)前端研制[D];電子科技大學(xué);2008年

4 王軼;基于DDS+PLL技術(shù)的高性能頻率源研究與實現(xiàn)[D];國防科學(xué)技術(shù)大學(xué);2004年

，

本文編號：1657656