本文選題：延時(shí)系統(tǒng)　切入點(diǎn)：鎖相環(huán)　出處：《電子科技大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：高精度大動(dòng)態(tài)延時(shí)系統(tǒng)在電子系統(tǒng)中有廣泛的應(yīng)用空間。延時(shí)電路的研究方法呈現(xiàn)多元化,主要分為光纖延時(shí)、模擬電路延時(shí)、數(shù)字電路延時(shí)。每一類延時(shí)方法都有各自的優(yōu)缺點(diǎn),很難同時(shí)滿足高精度、大動(dòng)態(tài)范圍、集成化等性能指標(biāo)。隨著FPGA技術(shù)的發(fā)展,提供了在器件內(nèi)部構(gòu)建高精度大動(dòng)態(tài)延時(shí)系統(tǒng)的條件。由于FPGA芯片的許多優(yōu)良特性,廣泛應(yīng)用于雷達(dá)系統(tǒng),延時(shí)系統(tǒng)與其他信號(hào)處理模塊集成于芯片內(nèi)部,將會(huì)有非常重要的工程意義。本文從實(shí)際工程應(yīng)用出發(fā),設(shè)計(jì)了一個(gè)對(duì)信號(hào)進(jìn)行高精度大動(dòng)態(tài)延時(shí)的系統(tǒng)。主要完成了以下工作。1.對(duì)延時(shí)電路的設(shè)計(jì)方案進(jìn)行了歸納總結(jié),得出高精度大動(dòng)態(tài)延時(shí)電路的設(shè)計(jì)思路,分為粗細(xì)延時(shí)的策略。將FPGA相關(guān)的延時(shí)方案進(jìn)行了深入的分析,總結(jié)了粗細(xì)延時(shí)在FPGA內(nèi)部實(shí)現(xiàn)的各種設(shè)計(jì)方法。通過(guò)對(duì)比各種方案,確立了延時(shí)系統(tǒng)的設(shè)計(jì)方案。對(duì)延時(shí)系統(tǒng)方案中影響精度的關(guān)鍵因素進(jìn)行了探討。2.延時(shí)系統(tǒng)設(shè)計(jì)方案中,核心的技術(shù)是對(duì)鎖相環(huán)進(jìn)行高精度相位調(diào)整操作。詳細(xì)分析了鎖相環(huán)的原理與結(jié)構(gòu),并對(duì)器件內(nèi)部嵌入的PLL結(jié)構(gòu)進(jìn)行了說(shuō)明。對(duì)掃描鏈中參數(shù)之間的關(guān)系進(jìn)行了梳理,重點(diǎn)介紹了鎖相環(huán)的重配置和動(dòng)態(tài)相位調(diào)整功能。3.結(jié)合工程指標(biāo),完成了高精度大動(dòng)態(tài)延時(shí)系統(tǒng)的整體設(shè)計(jì)與實(shí)現(xiàn),包括計(jì)數(shù)器延時(shí)模塊、具有動(dòng)態(tài)相位調(diào)整功能的鎖相環(huán)模塊,同頻異相采樣模塊,線性調(diào)頻信號(hào)產(chǎn)生模塊,串口通信模塊。對(duì)每一模塊的設(shè)計(jì)原理和方法都做了說(shuō)明。解決了異步時(shí)鐘采樣產(chǎn)生亞穩(wěn)態(tài)的問(wèn)題。4.基于FPGA開(kāi)發(fā)板,將整個(gè)延時(shí)系統(tǒng)的每一個(gè)模塊都做了細(xì)致的分析。利用仿真軟件對(duì)延時(shí)系統(tǒng)的高精度實(shí)現(xiàn)做了精確的分析。通過(guò)改變延時(shí)量,進(jìn)行多次測(cè)量,分析出延時(shí)系統(tǒng)的誤差量,并總結(jié)出誤差的來(lái)源。驗(yàn)證了設(shè)計(jì)的合理性與正確性。延時(shí)系統(tǒng)達(dá)到了性能指標(biāo)。
[Abstract]:High precision and large dynamic delay system has wide application space in electronic system. The research methods of delay circuit are diversified, mainly divided into optical fiber delay, analog circuit delay, Digital circuit delay. Each type of delay methods have their own advantages and disadvantages, it is difficult to meet the high accuracy, large dynamic range, integration and other performance indicators. With the development of FPGA technology, The condition of constructing high precision and large dynamic delay system inside the device is provided. Because of many excellent characteristics of FPGA chip, it is widely used in radar system, and the delay system is integrated with other signal processing modules inside the chip. This paper designs a system of high precision and large dynamic delay for signal. 1. The design scheme of delay circuit is summarized. The design idea of high precision and large dynamic delay circuit is obtained, which is divided into thick and fine delay strategy. The delay schemes related to FPGA are analyzed deeply, and various design methods of realizing thick and fine delay in FPGA are summarized. The design scheme of the delay system is established. The key factors influencing the precision of the delay system scheme are discussed. 2. In the design scheme of the delay system, The key technology is to adjust the phase of PLL with high precision. The principle and structure of PLL are analyzed in detail, and the embedded PLL structure is explained. The reconfiguration of PLL and the function of dynamic phase adjustment. 3. Combined with engineering indexes, the overall design and implementation of high precision and large dynamic delay system are completed, including counter delay module. Phase-locked loop module with dynamic phase adjustment function, same frequency and different phase sampling module, linear frequency modulation signal generating module, Serial communication module. The design principle and method of each module are explained. The problem of asynchronous clock sampling to produce metastable state is solved. 4. Based on FPGA development board, Each module of the whole delay system is analyzed in detail. The high precision realization of the delay system is analyzed accurately by using the simulation software. The error of the delay system is analyzed by changing the delay quantity and measuring it many times. The source of the error is summarized. The rationality and correctness of the design are verified. The delay system achieves the performance index.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN791

【參考文獻(xiàn)】

相關(guān)期刊論文 前2條

1 邱有剛;黃建國(guó);李力;;基于FPGA數(shù)字延遲單元的實(shí)現(xiàn)和比較[J];電子測(cè)量技術(shù);2011年09期

2 喬先科;謝方方;王莉靜;;基于PLL重配置技術(shù)的正交調(diào)制器設(shè)計(jì)[J];國(guó)外電子測(cè)量技術(shù);2014年06期

相關(guān)碩士學(xué)位論文 前1條

1 黃海艦;基于FPGA時(shí)間內(nèi)插技術(shù)的TDC設(shè)計(jì)[D];華中師范大學(xué);2013年

，

本文編號(hào)：1629245