本文選題：圖像傳感器　切入點(diǎn)：逐次逼近模數(shù)轉(zhuǎn)換器　出處：《吉林大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：圖像傳感器是一種將光學(xué)圖像轉(zhuǎn)換為電子信號的設(shè)備，是集像素陣列、模擬電路、數(shù)字電路于一體的數(shù)混合集成電路。根據(jù)最新的市場調(diào)查報告，從2014年到2020年，圖像傳感器產(chǎn)業(yè)將以10.6%的年均復(fù)合增長率快速增長，在2020年預(yù)計(jì)將達(dá)到160億美元的市場價值。在這龐大的市場中有很多領(lǐng)域需要高速圖像傳感器，比如科學(xué)研究、撞擊測試、高速掃描、機(jī)器視覺、軍事研究等等。 通常來說，圖像傳感器中應(yīng)用的是斜坡模數(shù)轉(zhuǎn)換器，然而由于其自身架構(gòu)的局限性，斜坡模數(shù)轉(zhuǎn)換器成為了高速圖像傳感器設(shè)計(jì)的瓶頸。在眾多其他類型的模數(shù)轉(zhuǎn)換器中，逐次逼近模數(shù)轉(zhuǎn)換器由于高精度、高速度、低功耗和面積小等優(yōu)勢而與圖像傳感器契合度更高，是設(shè)計(jì)高速CMOS圖像傳感器時的首選。 因而本課題在高速圖像傳感器的應(yīng)用背景下，設(shè)計(jì)了一款10bit20MS/s的全差分SAR ADC。它主要由采樣保持電路、比較器、異步時鐘產(chǎn)生電路、SAR邏輯控制模塊和DAC組成。通過對架構(gòu)的優(yōu)化，本課題設(shè)計(jì)的逐次逼近模數(shù)轉(zhuǎn)換器相比于傳統(tǒng)的逐次逼近模數(shù)轉(zhuǎn)換器要減少一半的電容，并且DAC中電容對應(yīng)的開關(guān)偏轉(zhuǎn)平均功耗僅為傳統(tǒng)架構(gòu)消耗能量的18.74%。 本論文設(shè)計(jì)的SAR ADC芯片在0.18um的CMOS工藝下，芯片面積為750x135um2；在1.8V的電源電壓下，芯片功耗為750uW。完成SARADC的版圖設(shè)計(jì)后，提取寄生，當(dāng)輸入信號頻率為566.4kHz時，得到的仿真結(jié)果如下：有效位數(shù)ENOB為9.89bit，信噪失真比SNDR為61.33dB，無雜散動態(tài)范圍SFDR為77.09dB。此外，還通過工藝角的仿真驗(yàn)證了上述結(jié)果的可靠性。對SARADC進(jìn)行流片，并搭建測試平臺，，當(dāng)輸入信號頻率為112kHz時，測得的結(jié)果如下：有效位數(shù)ENOB為8.63bit，信噪失真比SNDR=53.76dB，無雜散動態(tài)范圍SFDR為67.31dB。
[Abstract]:Image sensor is a device for converting optical image into electronic signal. It is a digital hybrid integrated circuit that integrates pixel array, analog circuit and digital circuit. According to the latest market research report, from 2014 to 2020, The image sensor industry is expected to grow rapidly at an annual compound growth rate of 10.6% and is expected to reach market value of $16 billion in 2020. There are many areas in this huge market that require high-speed image sensors, such as scientific research and impact testing. High-speed scanning, machine vision, military research, etc. Generally speaking, slope A / D converters are used in image sensors. However, because of the limitations of their own architecture, sloping analog-to-digital converters have become the bottleneck in the design of high speed image sensors. Because of the advantages of high precision, high speed, low power consumption and small area, the successive approximation A / D converters are more suitable for image sensors, which is the first choice in the design of high speed CMOS image sensors. Therefore, under the background of high speed image sensor, a 10 bit 20 MS / s fully differential SAR ADCs is designed. It consists of sampling and holding circuit, comparator, asynchronous clock generator circuit and DAC logic control module. Compared with the conventional successive approximation A / D converters designed in this paper reduce the capacitance by half and the average power consumption of the switches corresponding to the capacitors in the DAC is only 18.74% of the energy consumed by the traditional architecture. The SARADC chip designed in this paper has an area of 750x135um2 under 0.18um CMOS process, and the chip power consumption is 750uW. after the layout design of SARADC is completed, the parasitism is extracted. When the input signal frequency is 566.4kHz, The simulation results are as follows: the effective bit number (ENOB) is 9.89 bit, the signal-noise-distortion ratio (SNDR) is 61.33 dB, and the non-spurious dynamic range (SFDR) is 77.09 dB. In addition, the reliability of the above results is verified by the simulation of the process angle. When the input signal frequency is 112kHz, the results are as follows: the effective bit number ENOB is 8.63 bit, the signal-noise-distortion ratio is 53.76 dB, and the SFDR is 67.31 dB in the non-spurious dynamic range.
【學(xué)位授予單位】：吉林大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN792;TP212

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