本文選題：時(shí)間數(shù)字轉(zhuǎn)換器　切入點(diǎn)：游標(biāo)延遲鏈　出處：《寧波大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：在過去的幾十年中,集成電路工藝技術(shù)得到很大發(fā)展,尺寸越來越低,集成度越來越高,功耗越來越小,對(duì)于集成電路設(shè)計(jì)做出很大貢獻(xiàn)。時(shí)間數(shù)字轉(zhuǎn)換器(TDC)也隨著這次發(fā)展得到很大提升,TDC在集成度、芯片面積、工作速度、功耗和測(cè)量分辨率都有很大提高。TDC在航空航天、激光雷達(dá)和高能物理等方面有著重要的作用。因此,設(shè)計(jì)出高分辨率的TDC有著重要的現(xiàn)實(shí)意義。本文通過對(duì)不同TDC結(jié)構(gòu)性能進(jìn)行分析,最終采用游標(biāo)延遲鏈型TDC結(jié)構(gòu),游標(biāo)延遲鏈型TDC可以達(dá)到高分辨率和寬時(shí)間測(cè)量范圍。同時(shí)對(duì)于TDC的開始和結(jié)束控制信號(hào)進(jìn)行了分析,沒有采用外部信號(hào)進(jìn)行直接控制,因?yàn)橥獠啃盘?hào)上升沿時(shí)間比較長(zhǎng),影響了TDC中門翻轉(zhuǎn)時(shí)間,從而增加了門延遲時(shí)間,降低了TDC的分辨率。分析了不同上升沿階躍信號(hào)在門延遲中的延遲時(shí)間,上升沿時(shí)間越短對(duì)應(yīng)的門延遲時(shí)間越短,通過內(nèi)部設(shè)計(jì)的電壓比較器輸出信號(hào)作為TDC的控制信號(hào)。通過這種方式就可以提高傳統(tǒng)游標(biāo)延遲鏈型TDC分辨率。對(duì)TDC總體框架圖和時(shí)序圖進(jìn)行了設(shè)計(jì)和分析,TDC電路主要包括電壓比較器電路、振蕩器電路、Arbiter電路和16進(jìn)制計(jì)數(shù)器電路。電壓比較器電路產(chǎn)生陡峭的階躍信號(hào)控制TDC開始和結(jié)束信號(hào);兩路振蕩器電路作為TDC游標(biāo)延時(shí)鏈;Arbiter電路精確判斷兩路信號(hào)相位相差5ps判決跳變;16進(jìn)制計(jì)數(shù)器電路擴(kuò)展TDC時(shí)間測(cè)量范圍。對(duì)于TDC電路中誤差轉(zhuǎn)移模型和反相器單元延時(shí)模型進(jìn)行了分析。針對(duì)高速TDC電路輸出可能出現(xiàn)誤碼或者丟碼的現(xiàn)象,設(shè)計(jì)了輸入端冗余消除電路、偽“01”消除電路和計(jì)數(shù)器防抖動(dòng)電路。最后分析了TDC中誤差影響,給出了直接校正和間接校正兩種方法對(duì)TDC進(jìn)行校準(zhǔn)。最后,在TSMC 180nm工藝下完成TDC設(shè)計(jì),利用Cadence Spectre工具對(duì)電路進(jìn)行仿真分析,得到TDC的分辨率為5.3ps,功耗為6.5mW,版圖面積為0.13mm2,動(dòng)態(tài)范圍為7.2ns。結(jié)果表明,TDC的性能良好,達(dá)到了預(yù)期設(shè)計(jì)目標(biāo)。
[Abstract]:In the past few decades, the integrated circuit technology has been greatly developed, the size is getting lower and lower, the integration level is getting higher and higher, the power consumption is getting smaller and smaller. TDC has been greatly improved in integration, chip area, working speed, power consumption and measurement resolution with the development of TDC in aeronautics and astronautics. Lidar and high energy physics play an important role. Therefore, the design of high resolution TDC has important practical significance. By analyzing the performance of different TDC structures, the Vernier delay chain TDC structure is adopted in this paper. Vernier delay chain TDC can achieve high resolution and wide time measurement range. At the same time, the start and end control signals of TDC are analyzed. The gate flipping time in TDC is affected, thus the gate delay time is increased and the resolution of TDC is reduced. The delay time of different rising edge step signals in gate delay is analyzed. The shorter the rising edge time is, the shorter the gate delay time is. The output signal of the voltage comparator designed internally is used as the control signal of the TDC. In this way, the resolution of the traditional Vernier delay chain TDC can be improved. The overall frame diagram and sequence diagram of the TDC are designed and analyzed. The circuit mainly includes voltage comparator circuit, Oscillator circuit arbitrer circuit and hexadecimal counter circuit. Voltage comparator circuit generates steep step signal to control TDC start and end signal; The two-channel oscillator circuit is used as the TDC Vernier delay chain arbitrer circuit to accurately judge the phase difference between two signals by 5 PS decision jump / hexadecimal counter circuit to extend the range of TDC time measurement. For the error transfer model and inverter single in TDC circuit. The meta-delay model is analyzed. The error or loss of code may occur in the output of high-speed TDC circuit. The redundancy elimination circuit of input terminal, pseudo-" 01 "cancellation circuit and counter anti-jitter circuit are designed. Finally, the effect of error in TDC is analyzed, and two methods of direct correction and indirect correction to calibrate TDC are given. The design of TDC is completed under the TSMC 180nm process. The circuit is simulated and analyzed by Cadence Spectre tool. The result shows that the resolution of TDC is 5.3 pss, the power consumption is 6.5 MW, the layout area is 0.13 mm ~ 2, and the dynamic range is 7.2 ns.The results show that the performance of TDC is good and the expected design goal is achieved.
【學(xué)位授予單位】：寧波大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN402

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