發(fā)布時(shí)間：2018-03-06 05:24

  本文選題：片上網(wǎng)絡(luò)　切入點(diǎn)：蟲孔交換　出處：《國防科學(xué)技術(shù)大學(xué)》2015年博士論文　論文類型：學(xué)位論文

【摘要】：隨著半導(dǎo)體技術(shù)的不斷進(jìn)步,單個(gè)芯片上能夠集成的處理單元越來越多。片上網(wǎng)絡(luò)作為實(shí)現(xiàn)這些處理單元間互連的基礎(chǔ)通信架構(gòu)受到了學(xué)術(shù)界和工業(yè)界的廣泛關(guān)注。硬件成本和通信性能是評價(jià)片上網(wǎng)絡(luò)可用性的兩個(gè)非常重要的指標(biāo),如何以較低的硬件成本設(shè)計(jì)出能夠滿足實(shí)際應(yīng)用需求的片上網(wǎng)絡(luò)結(jié)構(gòu)是該領(lǐng)域研究的核心問題。本文針對片上網(wǎng)絡(luò)結(jié)構(gòu)設(shè)計(jì)與性能分析中幾個(gè)關(guān)鍵問題展開研究,主要的研究工作如下:(1)支持端口間緩存和虛通道共享的路由器微體系結(jié)構(gòu)研究虛通道蟲孔交換片上網(wǎng)絡(luò)的性能、功耗和硬件成本都會(huì)受到虛通道數(shù)量、緩存容量和緩存組織方式的影響。為了在不引入較大的硬件開銷和功耗負(fù)擔(dān)的前提下最大化片上網(wǎng)絡(luò)的性能,需要盡可能地提高路由器緩存資源的利用率。這就要求對緩存資源進(jìn)行動(dòng)態(tài)的分配和管理,以適應(yīng)片上網(wǎng)絡(luò)流量的動(dòng)態(tài)變化�，F(xiàn)有的方案基本都是圍繞著如何在路由器的端口之間或者端口內(nèi)的虛通道之間實(shí)現(xiàn)緩存資源的共享,忽略了不同端口對虛通道數(shù)量的不同需求以及需求的動(dòng)態(tài)變化。為此,本文提出了一種支持端口間自適應(yīng)虛通道共享(Adaptive Virtual Channel Sharing,AVCS)的路由器微體系結(jié)構(gòu),該結(jié)構(gòu)可以在運(yùn)行時(shí)根據(jù)網(wǎng)絡(luò)流量的變化動(dòng)態(tài)地調(diào)整每個(gè)路由器端口所能使用的緩存容量和虛通道數(shù)量。首先,本文分析了經(jīng)典路由器存在的主要問題,并針對這些問題提出了AVCS路由器的基本架構(gòu)。然后,本文面向AVCS路由器提出一個(gè)低成本的共享資源分配算法,該算法可以在運(yùn)行時(shí)將共享緩存資源按需分配給各個(gè)端口使用。最后,本文又面向AVCS路由器提出了一個(gè)虛通道和交換機(jī)分配器請求端口共享方案,該方案讓每個(gè)端口的私有虛通道與對應(yīng)的共享虛通道復(fù)用同一個(gè)虛通道和交換機(jī)分配器的請求端口,從而顯著地降低了分配器的規(guī)模和硬件成本。本文提出的AVCS路由器具有緩存資源利用率高、硬件開銷小和平均延遲低等優(yōu)點(diǎn)。實(shí)驗(yàn)結(jié)果顯示,與具有同樣性能的經(jīng)典路由器結(jié)構(gòu)相比,AVCS路由器可以降低32.1%的功耗并節(jié)省11.7%的芯片面積。(2)基于實(shí)時(shí)演算的片上網(wǎng)絡(luò)端到端延遲上界分析方法研究在基于片上網(wǎng)絡(luò)的多核處理器系統(tǒng)上部署實(shí)時(shí)應(yīng)用程序之前,必須要保證每條數(shù)據(jù)流在最差情況下的延遲上界都不違背其時(shí)限約束。針對這一需求,學(xué)術(shù)界已經(jīng)提出了基于確定性網(wǎng)絡(luò)演算的分析方法、基于流的分析方法和基于鏈路的分析方法來分析數(shù)據(jù)流的端到端延遲上界。然而,基于流和基于鏈路的分析方法都只能應(yīng)用于路由器的緩存容量足夠大的情況�；诰W(wǎng)絡(luò)演算的分析方法雖然沒有對緩存容量做任何假設(shè),但是獲得的延遲上界比較悲觀,需要進(jìn)一步地改進(jìn)。為此,本文提出一個(gè)基于實(shí)時(shí)演算的端到端延遲分析算法來克服基于流和基于鏈路的延遲分析方法的應(yīng)用限制,并進(jìn)一步改進(jìn)確定性網(wǎng)絡(luò)演算的分析結(jié)果。首先,本文提出一個(gè)流量模型變換定理用于將切片級實(shí)時(shí)演算到達(dá)曲線變換成報(bào)文級實(shí)時(shí)演算到達(dá)曲線,該定理使得對報(bào)文級端到端延遲上界的分析成為可能;然后,本文為蟲孔交換片上網(wǎng)絡(luò)建立了一個(gè)實(shí)時(shí)服務(wù)曲線模型,并利用極小加代數(shù)的有關(guān)性質(zhì)推導(dǎo)出了信約流量控制器的等效實(shí)時(shí)服務(wù)曲線;最后,本文基于前面建立的報(bào)文級實(shí)時(shí)到達(dá)曲線模型和路由器的實(shí)時(shí)服務(wù)曲線模型提出了一個(gè)端到端延遲分析算法。與已有的方法相比,該算法同時(shí)支持固定優(yōu)先級搶占調(diào)度和輪詢調(diào)度,對于緩存容量有限的片上網(wǎng)絡(luò)也能給出正確的分析結(jié)果,并且獲得的延遲上界比已有的方法更加緊致。(3)基于實(shí)時(shí)演算的片上網(wǎng)絡(luò)緩存分配算法研究路由器的緩存容量對整個(gè)片上網(wǎng)絡(luò)的性能、功耗和硬件成本都有巨大的影響。為了降低基于優(yōu)先級的蟲孔交換片上網(wǎng)絡(luò)的硬件成本,學(xué)術(shù)界已經(jīng)提出了虛通道共享方案和基于鏈路的緩存分配算法。然而,虛通道共享方案會(huì)嚴(yán)重影響網(wǎng)絡(luò)的通信性能,而且在特定的路由策略下還會(huì)引起死鎖。基于鏈路的緩存分配算法雖然可以保證網(wǎng)絡(luò)的通信性能,但是緩存分配結(jié)果過于保守。為此,本文提出一種基于實(shí)時(shí)演算的片上網(wǎng)絡(luò)緩存分配算法來降低基于優(yōu)先級的蟲孔交換片上網(wǎng)絡(luò)的硬件成本。該算法在保證時(shí)限約束的前提下,按照優(yōu)先級順序優(yōu)化每條數(shù)據(jù)流在其經(jīng)過的路由器上預(yù)留的緩存資源。首先,本文基于實(shí)時(shí)演算理論給出了每條數(shù)據(jù)流在其經(jīng)過的每個(gè)路由器上都不觸發(fā)流量控制的一個(gè)充分條件,該條件可以用于確定整個(gè)緩存優(yōu)化算法的迭代初始值;然后,本文給出了一個(gè)緩存分配過程來減少路由器為每條數(shù)據(jù)流預(yù)留的緩存資源,并結(jié)合前面給出的迭代初值定理提出了一個(gè)可以確保最差情況下通信性能的緩存分配算法。與已有的緩存分配算法相比,本文提出的算法可以顯著地降低路由器的硬件開銷,極大地降低路由器的硬件成本、功耗和芯片面積。(4)低延遲路徑選擇算法及其快速驗(yàn)證技術(shù)研究在蟲孔交換片上網(wǎng)絡(luò)中,每條數(shù)據(jù)流的端到端延遲都會(huì)受到網(wǎng)絡(luò)中其它數(shù)據(jù)流的傳輸路徑和流量特性的影響。因此,在為高優(yōu)先級數(shù)據(jù)流確定傳輸路徑時(shí)應(yīng)當(dāng)盡量選擇那些對低優(yōu)先級數(shù)據(jù)流影響較小的鏈路,以盡可能的優(yōu)化每一條數(shù)據(jù)流的端到端延遲。在確定了所有數(shù)據(jù)流的傳輸路徑之后,還需要一種有效的延遲分析方法來快速地確定是否每條數(shù)據(jù)流的延遲約束都得到了滿足。如果有數(shù)據(jù)流違背延遲約束,則應(yīng)該嘗試為其選擇一條新的傳輸路徑。針對上述需求,本文提出了一種面向Mesh網(wǎng)絡(luò)的低延遲路徑選擇算法來優(yōu)化每條數(shù)據(jù)流的端到端延遲。首先,該算法根據(jù)每條鏈路對低優(yōu)先級數(shù)據(jù)流的重要性程度為其賦予不同的權(quán)重。在確定鏈路的權(quán)重時(shí),該算法充分利用了Mesh網(wǎng)絡(luò)的基本性質(zhì)和組合數(shù)學(xué)的相關(guān)方法,大幅度地降低了已有方法的計(jì)算復(fù)雜度和存儲(chǔ)開銷。然后,該算法利用Dijkstra算法為每個(gè)數(shù)據(jù)流選擇一條合適的傳輸路徑。最后,該算法又利用之前提出的基于實(shí)時(shí)演算的延遲分析算法對每條數(shù)據(jù)流的延遲約束進(jìn)行檢查。為了加快延遲約束的檢查速度,本文還并針對延遲分析算法的性能優(yōu)化提出了若干建議。實(shí)驗(yàn)結(jié)果表明,本文提出的路徑選擇算法可以顯著地降低數(shù)據(jù)流的延遲上界。綜上所述,本文針對當(dāng)前片上網(wǎng)絡(luò)領(lǐng)域面臨的幾個(gè)重要問題進(jìn)行了研究,對推動(dòng)片上網(wǎng)絡(luò)在片上多處理器系統(tǒng)中的更廣泛的應(yīng)用具有一定的理論貢獻(xiàn)和應(yīng)用價(jià)值。
[Abstract]:With the development of semiconductor technology, a single chip can be integrated with the processing unit. More and more network on chip communication architecture as the foundation of realizing interconnection between the processing units has attracted wide attention in both academia and industry. The cost of hardware and communication performance evaluation are two very important indicators on the availability of the network, how to with a lower cost of hardware design can meet the practical needs of the on-chip network structure is a key problem in the research field. In this paper several key issues of structural design and performance analysis of network on chip in the study, the main research work is as follows: (1) the support router microarchitecture of virtual channel buffer and worm virtual channel sharing inter port hole exchange network on chip performance, power consumption and hardware cost are affected by the effect of virtual channel number, cache capacity and cache organization. For The performance of the network maximum on the premise of not introducing hardware overhead and power consumption of the larger burden, as far as possible need to improve the utilization rate of resources. This router cache requires allocation and dynamic management of cache resources, in order to adapt to the dynamic network traffic change on the existing schemes are basically. Around how to realize the sharing of cache resources between the router ports or ports within the virtual channel, ignore the dynamic changes of different needs of different number of ports on the virtual channels and demand. Therefore, this paper proposes an adaptive virtual channel sharing support between ports (Adaptive Virtual Channel Sharing, AVCS) router micro system the structure, cache capacity and virtual channel number of the structure can be run in accordance with the dynamic change of network traffic to adjust each router port to use. Firstly, this paper Analysis of the main problems of classical routers exist, and proposes the basic framework of AVCS router to solve these problems. Then, this paper proposes AVCS oriented router shared resource allocation algorithm for a low cost, the algorithm runtime shared cache resource allocation on demand for each port can be used again. Finally, this paper proposes a virtual channel and distributor switch request port sharing scheme for AVCS router, the virtual channel multiplexing scheme for sharing request with a virtual channel switch and distributor end private virtual channel for each port and the corresponding port, thereby reducing the size and cost of hardware distributor significantly. AVCS router is proposed in this paper has the cache resource utilization high, low hardware overhead and average delay etc.. Experimental results show that compared with the classical router structure has the same performance, AVCS router 32.1% can reduce power consumption and save 11.7% of the chip area. (2) to end delay method based on real-time applications before deployment of multi-core processor system on chip network based on real-time network analysis of upper bound on end, must ensure that each data flow delay bound in the worst case are not contrary to the time constraint. In response to this demand, the academic circle has put forward analysis method of deterministic network calculus based on flow analysis method and analysis method based on link analysis to data stream based on end-to-end delay bound. However, the cache capacity and flow analysis method based on link can only be applied to the router's big enough based on the analysis method based on network calculus. Although not make any assumptions on the cache capacity, but the delay bound is pessimistic, need further improvement. Therefore, this paper provided A real-time based end to end delay analysis algorithm to overcome the flow based and application based on the limit analysis method of link delay, analysis results and further improved deterministic network calculus. Firstly, this paper proposes a traffic model transformation theorem for the slice real-time arrival curve will transform into the message level real-time arrival curve the theorem of the message level, the end-to-end delay bound analysis becomes possible; then, the on-chip network established a real-time service model for wormhole switching curve, and using the minimum plus algebra is equivalent to the real-time service curve off nature derived letter about flow controller; finally, this paper established the front message level real-time arrival of real-time service curve model and the router presents an end-to-end delay analysis based algorithm. Compared with the existing methods, the proposed algorithm At the same time support fixed priority preemptive scheduling and scheduling, can give the correct results for the network on-chip cache capacity is limited, and the delay bound is more compact than the existing methods. (3) the performance of the cache capacity real-time network on chip cache allocation algorithm of the router based on the network. Have a great impact. In order to reduce the hardware cost and power consumption based on wormhole priority exchange network on chip hardware cost, the academic circle has put forward the virtual channel sharing scheme based on cache allocation algorithm and link. However, the communication performance of virtual channel sharing scheme will seriously affect the network, but also in particular the routing strategy cause a deadlock. Although the cache allocation algorithm can guarantee the communication link performance based on network, but the cache allocation is too conservative. Therefore, this paper proposes a Real-time network on chip cache allocation algorithm based on priority reduction based on wormhole exchange network on chip hardware cost. The algorithm not only guarantees the time constraint, according to the priority sequence optimization of each data flow through the router in its reserved cache resources. Firstly, the real-time theory gives each data flow at each router by the trigger is not a sufficient condition based on flow control, the conditions can be used to determine the initial value of iteration cache optimization algorithm; then, this paper presents a cache allocation process to reduce the router flow cache resource reservation for each data, and combined with the iterative initial value theorem given above propose a cache allocation algorithm can ensure the communication performance in the worst case. Compared with the existing cache allocation algorithm, this algorithm can Reduce the router hardware overhead significantly, greatly reduce the hardware cost of the router, the power consumption and chip area. (4) low delay path selection algorithm and fast verification technology research on wormhole switching network on chip, effects of each data flow end-to-end delay will be the transmission path and flow characteristics of other data flow network in. Therefore, in determining the transmission path for high priority data stream should try to choose those flow smaller link to the low priority data, with each data flow optimization possible end-to-end delay. After all the data transmission path was established, also need an effective delay the analysis method to quickly determine whether the delay constraint of each data flow are satisfied. If the data stream violates the delay constraint, you should try to choose a new transmission path for its on. The demand, this paper proposes a Mesh based low delay path selection algorithm to optimize each data flow end-to-end delay. Firstly, the algorithm according to the degree of importance of each link of the low priority data stream is given different weights. In the process of determining the weight of link, the algorithm makes full use of related methods the basic properties of combinatorial mathematics and Mesh network, greatly reduces the computational complexity of the existing methods and storage overhead. Then, the algorithm uses Dijkstra algorithm to select a suitable transmission path for each data stream. Finally, put forward the algorithm and use before real-time delay delay constraint algorithm for each data analysis flow check. Based on the delay constraint in order to speed up the examination speed, this paper aiming at the delay performance analysis optimization algorithm and put forward some suggestions. The experimental results show that the This paper puts forward the path selection algorithm can significantly reduce the delay bound in data streams. In summary, this paper studies several important problems on the network in the field of film, to promote the network on chip on chip in a multi processor system is more widely used and has certain theoretical contribution and practical value.

【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：博士
【學(xué)位授予年份】：2015
【分類號】：TN47

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