本文選題：流水線ADC　切入點(diǎn)：自適應(yīng)LMS算法　出處：《華南理工大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：流水線ADC(Analog to Digital Conversion,ADC)以其高速度、高精度、低功耗等特性被廣泛應(yīng)用于高分辨率數(shù)字圖像處理、視頻處理以及寬帶無線通信等領(lǐng)域。但是,隨著集成電路工藝的發(fā)展,電源電壓持續(xù)按比例縮小,運(yùn)放有限增益、非線性誤差、電容失配等非理想因素對(duì)流水線型ADC的性能提高帶來了極大挑戰(zhàn)。運(yùn)用數(shù)字域的校準(zhǔn)技術(shù)提高ADC的性能成為了近年的研究熱點(diǎn)。本文分析了線性和非線性誤差對(duì)流水線ADC的影響以及目前常用的校準(zhǔn)流水線ADC線性和非線性誤差的各種方法。針對(duì)基于參考ADC的數(shù)字后端校準(zhǔn)算法中存在的一些缺點(diǎn),即主信號(hào)通路和參考信號(hào)通路不同步會(huì)造成流水線ADC精度下降,同時(shí)主信號(hào)通路需要降頻會(huì)引起流水線ADC設(shè)計(jì)復(fù)雜度上升,本文設(shè)計(jì)了一個(gè)精度比較高的流水線子級(jí)代替參考ADC,對(duì)流水線ADC的各個(gè)子級(jí)校準(zhǔn)代替對(duì)整個(gè)ADC本身的校準(zhǔn),較好地解決了主信號(hào)通路和參考ADC信號(hào)通路不同步的缺點(diǎn),且該校準(zhǔn)系統(tǒng)不需要降頻同步。本文在Cadence Spectre設(shè)計(jì)平臺(tái)上設(shè)計(jì)并實(shí)現(xiàn)了冗余子級(jí)校準(zhǔn)系統(tǒng)中開關(guān)電路、兩相非交疊時(shí)鐘電路、比較器電路、運(yùn)算放大器電路、子級(jí)ADC電路和MDAC電路等關(guān)鍵模塊。在Matlab/Simulink中搭建了16-bit采樣頻率為10MSPS的流水線ADC模型,仿真結(jié)果表明,當(dāng)輸入信號(hào)頻率為4.7605MHz時(shí),經(jīng)過校準(zhǔn)后,流水線ADC的有效位和無雜散動(dòng)態(tài)范圍分別由9.37-bit、59.96d B提高到了校準(zhǔn)后的15.32-bit、99.55d B。最后利用Altera公司的Cyclone系列EP4CE22F17C6N器件進(jìn)行FPGA硬件驗(yàn)證,當(dāng)輸入信號(hào)頻率為4.7605MHz時(shí),頻譜分析表明流水線ADC的有效位和無雜散動(dòng)態(tài)范圍分別為12.73-bit和98.62d B,初步驗(yàn)證了基于冗余子級(jí)的后端校準(zhǔn)算法的可行性。
[Abstract]:Pipeline ADC(Analog to Digital conversion ADC(Analog is widely used in many fields such as high resolution digital image processing, video processing and wideband wireless communication due to its high speed, high precision and low power consumption. However, with the development of integrated circuit technology, Constant proportional reduction of power supply voltage, limited gain of operational amplifier, nonlinear error, The non-ideal factors such as capacitor mismatch have brought great challenge to the performance improvement of pipeline type ADC. The application of digital domain calibration technology to improve the performance of ADC has become a hot research topic in recent years. The linear and nonlinear error pairs are analyzed in this paper. The influence of pipeline ADC and the various methods of calibrating the linear and nonlinear errors of pipeline ADC. Some shortcomings of the digital back-end calibration algorithm based on reference ADC are pointed out. That is, if the main signal path and the reference signal path are not synchronized, the accuracy of pipeline ADC will be decreased, and the need for the main signal path to reduce the frequency will lead to the increase of the complexity in the design of pipeline ADC. In this paper, we design a high precision pipeline sub-level instead of reference ADC, and replace the whole ADC with every sublevel calibration of pipeline ADC, which solves the disadvantage of the synchronization between the main signal path and the reference ADC signal path. In this paper, the switching circuit, the two-phase non-overlapping clock circuit, the comparator circuit and the operational amplifier circuit in the redundant sub-level calibration system are designed and implemented on the Cadence Spectre design platform. Pipeline ADC model with 16-bit sampling frequency of 10MSPS is built in Matlab/Simulink. The simulation results show that when the input signal frequency is 4.7605MHz, the model is calibrated. The effective bit and non-stray dynamic range of pipeline ADC are increased from 9.37-bitn 59.96dB to 15.32-bitmong 99.55dB, respectively. Finally, the FPGA hardware is verified by Altera's Cyclone series EP4CE22F17C6N devices. When the input frequency is 4.7605MHz, the frequency of input signal is 4.7605MHz. Spectrum analysis shows that the effective bit and non-spurious dynamic range of pipeline ADC are 12.73-bit and 98.62dB, respectively. The feasibility of back-end calibration algorithm based on redundant sub-level is preliminarily verified.
【學(xué)位授予單位】：華南理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN792

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