本文關(guān)鍵詞： 編程器 FPGA USB JTAG 邊界掃描測試技術(shù)　出處：《哈爾濱工業(yè)大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著超大規(guī)模集成電路(Very Large Scale Integration,VLSI)技術(shù)的迅速發(fā)展,包括現(xiàn)場可編程邏輯器件(Field Programmable Gate Array,FPGA)與復(fù)雜可編程邏輯邏輯器件(Complex Programmable Logic Device,CPLD),因具有在線編程的獨(dú)特功能,廣泛應(yīng)用于航空航天、網(wǎng)絡(luò)通信、軍用雷達(dá)、儀器儀表、工業(yè)控制、醫(yī)用CT、家用電器、手機(jī)和計算機(jī)等各個領(lǐng)域,使傳統(tǒng)設(shè)計方法正在進(jìn)行一場巨大的變革。然而FPGA和CPLD得到廣泛應(yīng)用的同時也給燒寫配置CPLD和FPGA的編程器提出了更高的挑戰(zhàn)。當(dāng)前,FPGA和CPLD的編程器主要有兩種:一種是基于并口的,一種是基于USB高速接口的,前者由于下載速度慢加之便攜式電腦已無并口已經(jīng)很少使用,后者由于其更高的數(shù)據(jù)傳輸速率和使用的方便性使其在性能上更優(yōu)越。但是由于USB接口的編程器價格昂貴,使得許多FPGA開發(fā)人員望而卻步。其次編程器功能單一,不能滿足使用者擴(kuò)展功能的需求。本文研究并設(shè)計了基于IEEE1149.1標(biāo)準(zhǔn)的FPGA/CPLD編程器,在深度解析JTAG標(biāo)準(zhǔn)協(xié)議、邊界掃描測試技術(shù)和USB總線技術(shù)的基礎(chǔ)上,選擇了Altera官方的可編程邏輯器件編程器作為研究對象,通過對其內(nèi)部工作流程進(jìn)行解析,得出了編程器的內(nèi)部工作機(jī)制,并采用以PIC處理器為控制器,完成了編程器電路的設(shè)計,實現(xiàn)了對FPGA/CPLD的編程配置功能。不同于當(dāng)前開發(fā)設(shè)計的可編程邏輯器件編程器,本論文中所設(shè)計的編程器硬件設(shè)計上更精簡且不用另行設(shè)計上位機(jī)軟件,直接采用Quartus II開發(fā)環(huán)境即可使用,另外由于本編程器采用了SPI設(shè)計JTAG狀態(tài)機(jī)的方案,編程配置速度比當(dāng)前的USB-Blaster更快;本編程器具有多種功能,除了具有高速編程配置可編程邏輯器件的功能能外,還具有多接口數(shù)據(jù)傳輸功能,并能夠通過自行開發(fā)設(shè)計的軟件直接操作數(shù)據(jù)傳輸。
[Abstract]:With the rapid development of very Large Scale Integration Large (VLSI) technology, including Field Programmable Gate FPGA (Field Programmable Logic device) and complex Programmable Logic device (CPLDG), Very Scale Integration (VLSI) technology has been widely used in aerospace industry due to its unique function of on-line programming. Network communications, military radar, instrumentation, industrial control, medical CTs, household appliances, mobile phones, computers and other fields, The traditional design method is undergoing a great change. However, while FPGA and CPLD are widely used, they also pose a higher challenge to writing programmers that are configured with CPLD and FPGA. Currently, there are two main types of programmers for FPGA and CPLD:. One is based on parallel ports, One is based on the USB high-speed interface, which is rarely used because of slow download speed and the lack of parallel ports for portable computers. The latter is superior in performance due to its higher data transmission rate and ease of use. But because of the high cost of the USB interface programmer, many FPGA developers are deterred. The FPGA/CPLD programmer based on IEEE1149.1 standard is researched and designed in this paper. Based on the deep parsing of JTAG standard protocol, boundary scan test technology and USB bus technology, this paper studies and designs a FPGA/CPLD programmer based on IEEE1149.1 standard, boundary scan test technology and USB bus technology. The Altera programmable logic device programmer is chosen as the research object. Through the analysis of its internal workflow, the internal working mechanism of the programmable logic device is obtained, and the PIC processor is used as the controller. The design of the programmable logic device circuit is completed, and the programming configuration function of FPGA/CPLD is realized. In this paper, the hardware design of the programmer is more concise and the upper computer software is not designed separately, and the Quartus II development environment can be used directly. In addition, the JTAG state machine is designed by SPI. The program configuration speed is faster than the current USB-Blaster, the programming device has many functions, besides the function of high speed programming configuration programmable logic device, it also has the function of multi-interface data transmission. And can be designed by self-development of software direct operation of data transmission.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN791

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本文編號：1555218