本文關(guān)鍵詞： JESD204B 串行接口 芯片互聯(lián) VLSI設(shè)計(jì)　出處：《中國地質(zhì)大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：鑒于數(shù)據(jù)進(jìn)出FPGA的速度與轉(zhuǎn)換器數(shù)據(jù)處理速度不匹配的問題,FPGA公司早已探討多年高速SerDes接口的話題,均已認(rèn)識到大而快的通道的必要性,進(jìn)而可以充分利用SerDes的帶寬優(yōu)勢。在這樣的背景下,JEDEC委員會于2011年發(fā)布了JESD204B協(xié)議,作為轉(zhuǎn)換器行業(yè)的最新標(biāo)準(zhǔn),其主要應(yīng)用于數(shù)據(jù)轉(zhuǎn)換器與邏輯器件(FPGA/ASIC)之間的高速串行接口。相比于傳統(tǒng)的CMOS接口和LVDS接口,JESD204B接口在引腳數(shù)目、功耗等多個方面具備顯著的優(yōu)勢,很好的解決了并行接口布局布線復(fù)雜以及系統(tǒng)中多芯片同步、多芯片間確定性時(shí)延的問題,為無線通信、醫(yī)療成像等現(xiàn)代高速信號處理領(lǐng)域的數(shù)據(jù)接口提供了有效的解決方案,業(yè)內(nèi)一致認(rèn)為基于JESD204B協(xié)議的高速串行轉(zhuǎn)換器接口是通信系統(tǒng)繼續(xù)提高數(shù)據(jù)傳輸速率的重要保障。JESD204B發(fā)布后,迅速引起了國際知名數(shù)據(jù)轉(zhuǎn)換器廠商的重視,經(jīng)過這幾年的研究發(fā)展,目前ADI、TI等公司均已經(jīng)發(fā)布多款內(nèi)部集成基于JESD204B協(xié)議接口的芯片,但在國內(nèi)暫無完全自主知識產(chǎn)權(quán)的產(chǎn)品出現(xiàn),且基本上是利用特殊工藝如GaAs(砷化鎵)工藝實(shí)現(xiàn)該接口電路。本文在深入理解JESD204B協(xié)議的基礎(chǔ)上,提出了一種基于該協(xié)議的高速Serdes接口的接收電路設(shè)計(jì)方案,設(shè)計(jì)內(nèi)容主要涵蓋了協(xié)議的數(shù)據(jù)鏈路層和傳輸層。該文研究思路為嚴(yán)格依據(jù)協(xié)議規(guī)范,結(jié)合已有的相關(guān)芯片手冊,將協(xié)議所包含的功能進(jìn)行合理的模塊劃分,最終得到完全符合協(xié)議要求的電路結(jié)構(gòu)。本方案為滿足高達(dá)10Gbps的通道速率,采取四路并行設(shè)計(jì)的方法,有效降低了最高時(shí)鐘頻率的要求;同時(shí),數(shù)據(jù)處理與同步控制分離的拓?fù)浣Y(jié)構(gòu)也顯著的提高了電路的運(yùn)行速度。針對于協(xié)議詳細(xì)規(guī)范的初始碼組同步、初始通道同步、字符替換、自同步加擾、8B10B編碼等關(guān)鍵技術(shù),本文均給出了具體的設(shè)計(jì)方案且進(jìn)行了詳細(xì)的描述。本文所提方案的各個模塊均已通過Modelsim功能仿真及Design Compiler電路綜合,結(jié)果表明該方案正確實(shí)現(xiàn)了協(xié)議規(guī)范的數(shù)據(jù)鏈路層和傳輸層的各種功能,且整體電路可以工作在250Mhz時(shí)鐘頻率以上,能夠匹配高達(dá)10Gbps的串行通道速率,基本達(dá)到了協(xié)議的要求。該文提出了一種較為完整的JESD204B接收電路的解決方案,為國內(nèi)JESD204B接口電路的自主設(shè)計(jì)提供了一種參考方案。
[Abstract]:In view of the mismatch between the speed of data entering and leaving FPGA and the speed of data processing of converters, the company has been discussing the topic of high-speed SerDes interface for many years and has realized the necessity of large and fast channels. In this context, the JEDEC Committee issued the JESD204B protocol in 2011 as the latest standard in the converter industry. It is mainly used in the high-speed serial interface between data converter and logic device FPGA / ASIC. Compared with the traditional CMOS interface and LVDS interface, JESD204B interface has remarkable advantages in many aspects, such as pin number, power consumption, etc. It solves the problems of complex layout and wiring of parallel interface, synchronization of multi-chip and deterministic delay between multi-chips in the system. It provides an effective solution for the data interface in modern high-speed signal processing fields such as wireless communication, medical imaging and so on. The industry agrees that the high-speed serial converter interface based on JESD204B protocol is an important guarantee for the communication system to continue to improve the data transmission rate. JESD204B has attracted the attention of well-known international data converter manufacturers and has been studied and developed over the past few years. At present, many internal integration chips based on JESD204B protocol interface have been released by Adi TI and other companies, but there are no completely independent intellectual property products in China. The interface circuit is realized by using special technology such as GaAs (GaAs) process. Based on the deep understanding of JESD204B protocol, this paper presents a design scheme of high-speed Serdes interface based on this protocol. The design mainly covers the data link layer and transmission layer of the protocol. In order to satisfy the channel rate of up to 10Gbps, the four-channel parallel design method is adopted to effectively reduce the requirement of the highest clock frequency. The topology of data processing and synchronization control also improves the speed of the circuit. The key technologies such as initial code group synchronization, initial channel synchronization, character replacement, self-synchronous scrambling 8B10B coding and so on, are discussed in detail. In this paper, specific design schemes are given and described in detail. Each module of the proposed scheme has been simulated by Modelsim function and synthesized by Design Compiler circuit. The results show that this scheme can realize all kinds of functions of data link layer and transmission layer correctly, and the whole circuit can work above 250 MHz clock frequency, and can match the serial channel rate of up to 10Gbps. In this paper, a more complete solution of JESD204B receiving circuit is proposed, which provides a reference scheme for the independent design of domestic JESD204B interface circuit.
【學(xué)位授予單位】：中國地質(zhì)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN702

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