本文關(guān)鍵詞： 橫向雙擴(kuò)散金屬氧化物半導(dǎo)體場(chǎng)效應(yīng)晶體管 擊穿電壓 比導(dǎo)通電阻 超級(jí)結(jié)　出處：《西安電子科技大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：橫向雙擴(kuò)散金屬氧化物半導(dǎo)體場(chǎng)效應(yīng)晶體管(Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor,LDMOS)由于源極、柵極、漏極這三個(gè)電極都分布在器件的同一表面,相較于縱向雙擴(kuò)散金屬氧化物半導(dǎo)體場(chǎng)效應(yīng)晶體管(Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor,VDMOS)而言,更容易與低壓電路信號(hào)通過(guò)內(nèi)部連接而實(shí)現(xiàn)集成,因此是實(shí)現(xiàn)功率集成電路(Power Integrated Circuit,PIC)的關(guān)鍵。功率集成電路(PIC)主要追求的指標(biāo)是低功耗,所以要求橫向雙擴(kuò)散MOS功率器件(LDMOS)的指標(biāo)是實(shí)現(xiàn)高擊穿電壓和低比導(dǎo)通電阻。當(dāng)前,國(guó)內(nèi)外對(duì)于橫向雙擴(kuò)散MOS功率器件主要的研究方向是:如何從新的結(jié)構(gòu),新的工藝,新的材料等方面對(duì)擊穿電壓和比導(dǎo)通電阻進(jìn)行優(yōu)化。本篇論文主要是從新結(jié)構(gòu)方面,對(duì)階梯狀場(chǎng)氧化層折疊硅新型橫向雙擴(kuò)散MOS功率器件和具有P型覆蓋層超級(jí)結(jié)橫向雙擴(kuò)散MOS功率器件這兩種新型橫向雙擴(kuò)散MOS功率器件的結(jié)構(gòu)、性能進(jìn)行分析與優(yōu)化,并且對(duì)工藝流程進(jìn)行了設(shè)計(jì)。首先,本論文提出了階梯狀場(chǎng)氧化層折疊硅新型橫向雙擴(kuò)散MOS功率器件(SOFLDMOS),這種結(jié)構(gòu)具有如下幾種特點(diǎn):第一,這種結(jié)構(gòu)是將硅刻蝕成周期性折疊形狀,使得柵極的導(dǎo)電區(qū)域增加,降低新型SOFLDMOS器件比導(dǎo)通電阻,這點(diǎn)原理類似于FinFET;第二,由于柵電極延伸到階梯狀場(chǎng)氧化層的表面,從而在正向?qū)〞r(shí)漂移區(qū)中產(chǎn)生多數(shù)載流子(電子)的積累層使得其比導(dǎo)通電阻降低。另外,由于新型SOFLDMOS器件是折疊形狀,因此在漂移區(qū)I區(qū)的兩個(gè)側(cè)壁也會(huì)形成電子的積累,使得漂移區(qū)積累層中電子的數(shù)量劇增,從而降低新型SOFLDMOS器件的比導(dǎo)通電阻;第三,由于新型SOFLDMOS器件是折疊結(jié)構(gòu),在關(guān)態(tài)時(shí)通過(guò)X和Y方向引入的電場(chǎng)調(diào)制作用(原理類似于超級(jí)結(jié))可以提高漂移區(qū)濃度,從而降低其比導(dǎo)通電阻;最后,將階梯狀場(chǎng)氧化層覆蓋在漂移區(qū)的表面,通過(guò)階梯狀場(chǎng)氧化層的電場(chǎng)調(diào)制作用使得SOFLDMOS的表面電場(chǎng)在其階梯處產(chǎn)生一個(gè)新的電場(chǎng)峰而使得表面電場(chǎng)分布趨于更加均勻。利用仿真軟件ISE-TCAD具體分析了各種參數(shù)對(duì)SOFLDMOS性能的影響,結(jié)果表明:通過(guò)優(yōu)化SOFLDMOS的主要參數(shù),實(shí)現(xiàn)了當(dāng)擊穿電壓在62V的條件下,獲得較低的比導(dǎo)通電阻為0.74mΩ.cm~2。在相同擊穿電壓情況下,其比導(dǎo)通電阻相較于傳統(tǒng)橫向雙擴(kuò)散MOS功率器件結(jié)構(gòu)的2mΩ.cm~2降低了63%左右。其次,本論文提出了具有P型覆蓋層超級(jí)結(jié)橫向雙擴(kuò)散MOS功率器件(P covered SJ-LDMOS),這種結(jié)構(gòu)是在傳統(tǒng)的N型緩沖層超級(jí)結(jié)橫向雙擴(kuò)散MOS功率器件結(jié)構(gòu)基礎(chǔ)上,其超級(jí)結(jié)區(qū)的N型柱表面部分?jǐn)U散(或離子注入)一層P型覆蓋層,利用P型覆蓋層與N型緩沖層的相互作用消除傳統(tǒng)超級(jí)結(jié)橫向雙擴(kuò)散MOS功率器件結(jié)構(gòu)存在的襯底輔助耗盡效應(yīng),同時(shí),由于N型緩沖層相當(dāng)于一條導(dǎo)通路徑,利用P型覆蓋層的電中性作用,提高N型緩沖層的摻雜濃度從而降低了P covered SJ-LDMOS器件的比導(dǎo)通電阻。利用仿真軟件ISE-TCAD具體分析了各種參數(shù)對(duì)P covered SJ-LDMOS性能的影響,結(jié)果表明:通過(guò)優(yōu)化P covered SJ-LDMOS的主要參數(shù),實(shí)現(xiàn)了當(dāng)擊穿電壓在203V的條件下,獲得4.26mΩ.cm~2的比導(dǎo)通電阻。在漂移區(qū)長(zhǎng)度都為10μm的情況下,具有P型覆蓋層超級(jí)結(jié)橫向雙擴(kuò)散MOS功率器件結(jié)構(gòu)的比導(dǎo)通電阻相較于傳統(tǒng)超級(jí)結(jié)橫向雙擴(kuò)散MOS功率器件結(jié)構(gòu)的10.47mΩ.cm~2降低了59%左右,相較于傳統(tǒng)具有N型緩沖層超級(jí)結(jié)橫向雙擴(kuò)散MOS功率器件的7.46mΩ.cm~2降低了43%左右。最后,對(duì)階梯狀場(chǎng)氧化層折疊硅新型橫向雙擴(kuò)散MOS功率器件與P型覆蓋層超級(jí)結(jié)橫向雙擴(kuò)散MOS功率器件這兩種器件的工藝流程進(jìn)行了設(shè)計(jì),同時(shí)對(duì)工藝難點(diǎn)進(jìn)行分析,并且給予解決方案。
[Abstract]:Lateral double diffused metal oxide semiconductor field effect transistor (Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor, LDMOS) as the source, gate, drain the three electrodes are distributed on the same surface of the device, compared to the vertical double diffused metal oxide semiconductor field effect transistor (Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor, VDMOS), and more easily low voltage circuit signal through the internal connection and integration, so is the integrated circuit power (Power Integrated Circuit, PIC). The key power integrated circuit (PIC) index is the main pursuit of low power consumption, so the lateral double diffused MOS power device (LDMOS) index is to achieve a high breakdown voltage and low conduction resistance at present, the research direction at home and abroad for lateral double diffused MOS main power device is: how to From the new structure, new technology, new materials and other aspects of the breakdown voltage and on resistance are optimized. This thesis is mainly from the new structure, the ladder shaped folding field oxide silicon new lateral double diffused MOS power devices and has the structure of P type layer super junction lateral double diffusion MOS the power device of the two new lateral double diffused MOS power device, performance analysis and optimization, and process design. Firstly, this thesis presents ladder folding field oxide silicon new lateral double diffused MOS power device (SOFLDMOS), this kind of structure has the following characteristics: first, the structure the silicon etching the periodic folded shape, the conductive gate region increase, reduce new SOFLDMOS devices on resistance, this principle is similar to FinFET; second, the gate electrode extends to the surface of terraced field oxide layer Thus, the majority of carriers in the forward conduction time in the drift region (E) of the accumulation layer makes its conduction resistance decreased. In addition, due to the new SOFLDMOS device is folded shape, so the two side wall in the drift region of the I area will be the formation of electron accumulation, the drift area increasing number of electron accumulation layer the new SOFLDMOS device so as to reduce the specific resistance; third, due to the new SOFLDMOS device is folded structure, through the electric field modulation into X and Y direction in the off state (principle similar to the super node) can improve the concentration of the drift region, thereby reducing the conduction resistance; finally, the surface of the ladder the shape of the field oxide layer in the drift region, the electric field modulation ladder field oxide layer makes the surface electric field of SOFLDMOS to produce a new electric field peak in the step of the surface electric field distribution tends to be more uniform by simulation. The software ISE-TCAD detailed analysis of the impact of various parameters on the performance of SOFLDMOS, the results show that the main parameters of the optimization of SOFLDMOS, realized when the breakdown voltage under the condition of 62V was lower than the resistance of 0.74M..cm~2. in the same breakdown voltage under the conduction resistance compared with the conventional lateral double diffusion MOS power device structure of 2m..cm~2 decreased about 63%. Secondly, this paper presents a P type super node layer lateral double diffused MOS power device (P covered SJ-LDMOS), the structure is in the N buffer layer, super node lateral double diffused MOS power device structure on the basis of the traditional surface N the column part of the super junction diffusion (or ion implantation) a layer of P covering layer, using the interaction between type P and type N overlay buffer layer to eliminate the traditional structure of super node lateral double diffused MOS power device substrate assisted consumption As far as effect, at the same time, because the N buffer layer is equivalent to a conduction path, using electrically neutral type P covering layer, improve the doping concentration of N buffer layer, which reduces the conduction resistance of P covered SJ-LDMOS device. A concrete analysis of the influence of various parameters on the performance of P covered SJ-LDMOS by simulation the software ISE-TCAD the results show that the main parameters optimization of P covered SJ-LDMOS, realized when the breakdown voltage under the condition of 203V, obtain the conduction resistance of 4.26M..cm~2. In the drift region length is 10 m, with P type structure covering layer of super node lateral double diffused MOS power devices than resistance compared with the traditional super node lateral double diffused MOS power device structure of 10.47m..cm~2 decreased by about 59%, compared with the traditional N type with buffer layer of super node lateral double diffused MOS power device 7.46m.Cm~2 is reduced by about 43% Finally, the process flow of two kinds of devices, the ladder type field oxide layer folded silicon new lateral double diffused MOS power device and the P overlay super junction double diffused MOS power device, are designed. Meanwhile, the technological difficulties are analyzed, and solutions are given.

【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN386

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