本文關(guān)鍵詞： 注入鎖定分頻器 鎖定范圍 壓控振蕩器 毫米波 電感建模　出處：《山東大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：當(dāng)前的各種無線通信技術(shù)因為頻譜資源日益緊張和傳輸速率有限而無法滿足應(yīng)用需求。毫米波通信技術(shù)的帶寬高達(dá)5-7GHz,傳輸速率可實現(xiàn)數(shù)Gbps,是當(dāng)前的研究熱點。同時,CMOS器件的高頻性能伴隨工藝的快速發(fā)展而不斷提高,低成本、高集成度、能與基帶工藝相集成等優(yōu)勢使得CMOS器件成為設(shè)計毫米波集成電路的理想選擇。壓控振蕩器和分頻器作為鎖相環(huán)頻率綜合器的核心部件,工作頻率最高,它們的性能好壞將直接影響整個收發(fā)系統(tǒng)的性能。本文基于SMIC 40nm CMOS工藝,設(shè)計了應(yīng)用于毫米波鎖相環(huán)的壓控振蕩器和注入鎖定分頻器,主要工作和成果包括如下方面：1、利用ADS和HFSS軟件,對應(yīng)用于毫米波頻段的無源器件電感和傳輸線進行了電磁仿真,優(yōu)化器件尺寸以滿足設(shè)計需求；建立電感的等效電路模型,方便設(shè)計優(yōu)化和提高仿真精度；分析比較了常見可變電容結(jié)構(gòu)的性能優(yōu)劣。2、基于SMIC 40nm CMOS工藝,設(shè)計了一種應(yīng)用于60GHz毫米波頻率綜合器的二分頻注入鎖定分頻器。通過優(yōu)化注入網(wǎng)絡(luò)和有源及無源器件尺寸等方法,提高了注入效率。電磁仿真設(shè)計并優(yōu)化無源電感以擴大鎖定范圍。優(yōu)化版圖設(shè)計減少了寄生、失配和干擾。后仿真結(jié)果表明,該分頻器工作頻率為55.2～61.2GHz,注入鎖定范圍為6.0GHz。電源電壓0.8V下,功耗為5.5mW(不計緩沖放大器),核心電路面積為0.016mm2。本設(shè)計實現(xiàn)了低功耗、芯片面積小和寬鎖定范圍的目標(biāo)。3、基于SMIC 40nm CMOS工藝,設(shè)計了一種低功耗寬調(diào)諧范圍的壓控振蕩器。采用分布式電感電容結(jié)構(gòu),提高振蕩頻率,降低振蕩所需的環(huán)路增益；優(yōu)化諧振網(wǎng)絡(luò)中電容的設(shè)計,降低相位噪聲,提高調(diào)諧范圍；電磁仿真無源電感,提高品質(zhì)因數(shù),降低相位噪聲。后仿真結(jié)果表明,壓控振蕩器頻率調(diào)諧范圍為56.1-61.2GHz(5.1GHz,8.7%),振蕩中心頻率處的相位噪聲為-88dBc/Hz@1MHz。電源電壓0.8V下,功耗為3.3mW(不計緩沖放大器)。芯片核心面積為0.0135mm2。將壓控振蕩器的輸出信號作為注入鎖定分頻器的輸入信號,分頻器對振蕩器的輸出頻率實現(xiàn)二分頻。壓控振蕩器和注入鎖定分頻器聯(lián)合仿真的結(jié)果驗證了相位噪聲理論,表明壓控振蕩器和分頻器的設(shè)計適用于毫米波鎖相環(huán)頻率綜合器。
[Abstract]:The current wireless communication technology is unable to meet the needs of application because of the growing shortage of spectrum resources and the limited transmission rate. The bandwidth of millimeter wave communication technology is up to 5-7 GHz, and the transmission rate can be realized by several Gbpss, which is the current research hotspot. The high frequency performance of CMOS devices has been improved with the rapid development of technology. The advantages of low cost, high integration, and the ability to integrate with baseband technology make CMOS an ideal choice for the design of millimeter-wave integrated circuits. VCO and frequency divider are the core components of PLL frequency synthesizer. Their performance will directly affect the performance of the whole transceiver system. Based on the SMIC 40nm CMOS process, a voltage-controlled oscillator and an injection-locked frequency divider are designed for millimeter wave phase-locked loop (MMW PLL). The main work and achievements are as follows: using ADS and HFSS software, the electromagnetic simulation of passive device inductor and transmission line applied in millimeter wave band is carried out to optimize the device size to meet the design requirements, and the equivalent circuit model of inductance is established. It is convenient to design, optimize and improve the simulation accuracy, and analyzes and compares the performance of common variable-capacitor structures. 2. Based on SMIC 40nm CMOS process, An injection locking frequency divider for 60GHz millimeter wave frequency synthesizer is designed. The injection network and the size of active and passive devices are optimized. The injection efficiency is improved. Electromagnetic simulation design and optimization of passive inductor are used to enlarge the locking range. The optimized layout design reduces parasitism, mismatch and interference. The simulation results show that, The frequency of the divider is 55.2 GHz, the injection locking range is 6.0 GHz, the power consumption is 5.5 MW at 0.8 V power supply voltage (excluding buffer amplifier, the core circuit area is 0.016 mm2.This design achieves low power consumption. Based on the SMIC 40nm CMOS process, a low power and wide tuning range voltage-controlled oscillator is designed based on the small area and wide locking range of the chip. A distributed inductance capacitor structure is used to increase the oscillation frequency and reduce the loop gain required for the oscillation. The design of capacitance in the resonant network is optimized to reduce the phase noise and the tuning range is increased, the passive inductance is simulated by electromagnetic simulation, the quality factor is improved, and the phase noise is reduced. The frequency tuning range of the VCO is 56.1-61.2GHz (5.1GHz) and the phase noise at the central frequency of the oscillator is -88dBc / HzR 1MHz. The power supply voltage is 0.8V. The power consumption is 3.3 MW (excluding buffer amplifier). The core area of the chip is 0.0135 mm2.The output signal of the VCO is used as the input signal of the injection-locked divider. The phase noise theory is verified by the simulation of the voltage-controlled oscillator and the injection-locked frequency divider, which indicates that the design of the voltage-controlled oscillator and the divider is suitable for the millimeter-wave phase-locked loop frequency synthesizer.
【學(xué)位授予單位】：山東大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN772

【參考文獻】

相關(guān)期刊論文 前1條

1 杜澤保;楊浩;張海英;;V波段CMOS注入鎖相二分頻器設(shè)計[J];中國科學(xué)院研究生院學(xué)報;2012年05期

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本文編號：1540499