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GLSI多層銅布線阻擋層CMP及其后清洗表面粗糙度的研究

發(fā)布時間:2018-02-24 18:26

  本文關(guān)鍵詞: 集成電路 化學(xué)機械拋光 阻擋層拋光液 清洗液 表面粗糙度 出處:《河北工業(yè)大學(xué)》2015年碩士論文 論文類型:學(xué)位論文


【摘要】:隨著集成電路技術(shù)的迅猛發(fā)展和進步,芯片的集成度越來越高,特征尺寸逐漸減小,線寬也越來越窄,對集成電路性能的要求越來越高,如提高集成度、解決互連延遲,還要滿足性能、頻寬和功耗的要求等。目前,國際上特征尺寸為22nm/20nm的極大規(guī)模集成電路(GLSI)已實現(xiàn)大規(guī)模生產(chǎn),晶圓尺寸為300mm,多層金屬互連層數(shù)高達10層以上,為了保證最終晶圓各種參數(shù)乃至器件性能滿足客戶的要求,就要求在每一層布線之后,都能夠得到較高的晶圓表面平整度。化學(xué)機械拋光(CMP)是目前公認(rèn)的能夠有效實現(xiàn)全局平坦化的技術(shù),而在集成電路制造過程所需要的CMP中,阻擋層的CMP是最終決定晶圓平坦化效果的關(guān)鍵環(huán)節(jié),直接影響器件性能和成品率。阻擋層的CMP過程涉及到對銅、鉭、介質(zhì)這三種不同性質(zhì)材料同時進行拋光,最終將鉭和介質(zhì)完全去除,剩余銅線條,由于銅質(zhì)地較軟,拋光后表面易產(chǎn)生微劃傷、腐蝕坑等問題,這都對阻擋層的CMP提出了更大的挑戰(zhàn),并且拋光后表面會有顆粒的粘附,這些問題都影響晶圓表面粗糙度。因此對阻擋層CMP過程以及清洗液進行深層次研究就有了非常重要的實踐意義。本文主要通過單因素實驗探索拋光工藝參數(shù)、拋光液組分及清洗液成分對銅表面粗糙度的影響,對實驗數(shù)據(jù)進行整理,對所得結(jié)果進行研究分析,并將研究的最后成果運用到300mm銅布線晶圓阻擋層平坦化實驗中。拋光后對實驗晶圓片進行表面缺陷的檢測,測試結(jié)果為拋光后單層銅布線碟形坑低于450?,蝕坑低于200?,銅膜表面粗糙度為0.679nm,各項檢測結(jié)果均滿足工業(yè)生產(chǎn)要求。實驗結(jié)果表明此弱堿性阻擋層拋光液實現(xiàn)阻擋層平坦化的可行性,并且其組分簡單,環(huán)保,易清洗,其中不含傳統(tǒng)增膜腐蝕抑制劑BTA,不含不穩(wěn)定的氧化劑成分,不存在酸性拋光液導(dǎo)致的腐蝕、成分復(fù)雜,成本高等問題。通過阻擋層CMP后清洗液的清洗,拋光片表面微缺陷密度與表面微粗糙度進一步降低,獲得了良好的表面形貌。
[Abstract]:With the rapid development and progress of the integrated circuit technology, the integration degree of the chip becomes higher and higher, the characteristic size decreases gradually, the line width becomes narrower and narrower, and the performance of the integrated circuit is required more and more, such as improving the integration level and solving the interconnect delay. It also needs to meet the requirements of performance, bandwidth and power consumption. At present, the international maximum scale integrated circuit (GLSI) with a characteristic size of 22nm / 20nm has been produced on a large scale, with a wafer size of 300mm and a multilayer metal interconnect layer of more than 10 layers. In order to ensure that the final wafer parameters and even device performance meet customer requirements, after each layer of wiring, Chemical mechanical polishing (CMP) is currently recognized as a technology that can effectively achieve global flatness, while in CMP, which is required for integrated circuit manufacturing, The CMP of the barrier layer is the key to determine the effect of wafer flattening, which directly affects the performance and the yield of the device. The CMP process of the barrier layer involves the simultaneous polishing of copper, tantalum and dielectric materials with different properties, such as copper, tantalum and dielectric. Finally, tantalum and media are removed completely, and the remaining copper wire strips are removed completely. Due to the softer quality of copper, the surface of polished copper is prone to be scratched, corrosion pits and so on. This poses a greater challenge to the CMP of the barrier layer, and there will be particle adhesion on the polished surface. All of these problems affect the surface roughness of wafer. Therefore, it is very important to study the CMP process of barrier layer and the cleaning liquid deeply. In this paper, single factor experiments are used to explore the polishing process parameters. The effects of the components of polishing liquid and cleaning liquid on the surface roughness of copper were analyzed. The final results of the study were applied to the experiment of flattening the barrier layer of 300mm copper wiring wafer. After polishing, the surface defects of the wafer were detected, and the results showed that the surface defect of the wafer was less than 450? , etch pit less than 200? The surface roughness of copper film is 0.679 nm, and all the test results meet the requirements of industrial production. The experimental results show that it is feasible to flatten the barrier layer by using this weakly alkaline barrier layer polishing liquid, and its composition is simple, environmental protection is easy, and it is easy to clean. There are no traditional corrosion inhibitor, no unstable oxidant, no corrosion caused by acid polishing liquid, complex composition, high cost and so on. The surface microdefect density and the surface microroughness of the polishing wafer were further reduced and the good surface morphology was obtained.
【學(xué)位授予單位】:河北工業(yè)大學(xué)
【學(xué)位級別】:碩士
【學(xué)位授予年份】:2015
【分類號】:TN405

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