本文關(guān)鍵詞： Verilog-A 電流舵 數(shù)模轉(zhuǎn)換器 數(shù)字自補(bǔ)償　出處：《北方工業(yè)大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：高速高精度的數(shù)模轉(zhuǎn)換器(DAC)是許多信號處理和通信系統(tǒng)至關(guān)重要的結(jié)構(gòu)模塊。電流舵型DAC由于自身結(jié)構(gòu)的優(yōu)越性成為了DAC設(shè)計(jì)者的首選。然而由于受到工藝偏差的影響產(chǎn)生的電流源不匹配以及高速情況下產(chǎn)生的時(shí)鐘饋通和時(shí)序誤差導(dǎo)致電流舵型DAC的性能受到了一定的制約。因此各種補(bǔ)償和校準(zhǔn)技術(shù)成為了設(shè)計(jì)者提高電流舵型DAC動(dòng)態(tài)性能的主要方法。對電路建模是一種高速有效的設(shè)計(jì)研究方法,它既可以對電路進(jìn)行輔助仿真,同時(shí)也可以對電路性能和參數(shù)進(jìn)行研究,對電路的搭建和設(shè)計(jì)有一定的指導(dǎo)作用。因此本文以14位200MHz電流舵型DAC為對象,重點(diǎn)針對電流源的失配對DAC的動(dòng)態(tài)范圍影響這個(gè)問題,從對電路建模并采用數(shù)字自補(bǔ)償技術(shù)對電路進(jìn)行校準(zhǔn)兩個(gè)方面對提高DAC的性能的方法和技術(shù)進(jìn)行了研究。 首先,對DAC的原理進(jìn)行了研究,具體的介紹和分析了常用的幾種DAC的結(jié)構(gòu)和優(yōu)缺點(diǎn),并對電流舵型DAC的三種結(jié)構(gòu)進(jìn)行詳細(xì)的介紹、分析和比較。其次,本文重點(diǎn)分析了電流源的非理想因素產(chǎn)生機(jī)理和影響以及高速下數(shù)字時(shí)鐘誤差產(chǎn)生的來源,并分析了電流源失配對DAC的動(dòng)態(tài)范圍的影響。然后,針對這些失配,利用Verilog-A語言建立對應(yīng)的模型,并將失配的電流源模型加入理想DAC模型中進(jìn)行仿真分析,研究失配對DAC性能的影響,從而指導(dǎo)電路設(shè)計(jì)。針對電路失配,本文采用RSTC的DEM數(shù)字自補(bǔ)償技術(shù)對電路進(jìn)行校準(zhǔn),然后進(jìn)行仿真驗(yàn)證。 本文利用CADENCE, Verilog, Verilog-A, Matlab等EDA軟件進(jìn)行驗(yàn)證。電路整體采用數(shù)�；旌戏抡娣绞竭M(jìn)行仿真,在輸入時(shí)鐘頻率為200MHz,信號頻率為0.9987MHz,14位理想DAC的SFDR為114dB；當(dāng)電流源隨機(jī)失配為0.1%情況下,DAC的SFDR為89dB。在0.1%的電流源失配電路中加入數(shù)字自補(bǔ)償電路后,電路的SFDR為97dB,驗(yàn)證了其實(shí)用性。
[Abstract]:High speed and high precision digital-to-analog converter (DAC) is one of the most important structural modules in many signal processing and communication systems. The current-rudder DAC has become the first choice for DAC designers because of its advantages in structure. However, due to the process bias, the current rudder DAC has become the first choice for DAC designers. The mismatch of current source and clock feedthrough and timing error at high speed have restricted the performance of current-rudder DAC. Therefore, various compensation and calibration techniques have become designers to improve electrical performance. The main method of dynamic performance of current rudder type DAC. The circuit modeling is a high speed and effective design method. It can not only simulate the circuit, but also study the performance and parameters of the circuit. It can guide the circuit construction and design. So this paper takes the 14-bit 200MHz current-rudder DAC as the object. Focusing on the effect of current source mismatch on the dynamic range of DAC, the methods and techniques to improve the performance of DAC are studied from two aspects: modeling the circuit and calibrating the circuit using digital self-compensation technology. Firstly, the principle of DAC is studied, the structure, advantages and disadvantages of several kinds of DAC are introduced and analyzed in detail, and the three structures of current rudder type DAC are introduced, analyzed and compared in detail. In this paper, the mechanism and influence of non-ideal factors of current source and the source of digital clock error at high speed are analyzed, and the influence of current source mismatch on the dynamic range of DAC is analyzed. The corresponding model is established by using Verilog-A language, and the mismatched current source model is added to the ideal DAC model for simulation analysis. The effect of mismatch on the performance of DAC is studied to guide the circuit design. In this paper, the DEM digital self-compensation technology of RSTC is used to calibrate the circuit, and then the simulation is carried out. In this paper, we use EDA software, such as CADENCEE, Verilog, Verilog-Aand Matlab, to verify the circuit. When the input clock frequency is 200MHz and the signal frequency is 0.9987MHz / 14, the SFDR of the ideal DAC is 114dB, and the SFDR of the current source is 89 dB when the random mismatch of the current source is 0.1%. The SFDR of the circuit is 97 dB after adding the digital self-compensation circuit to the current source mismatch circuit of 0.1%, which verifies its practicability.
【學(xué)位授予單位】：北方工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN792

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本文編號：1514544