本文關(guān)鍵詞： JPEG2000 MQ解碼器 FPGA 高級綜合　出處：《西安電子科技大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：JPEG2000標準是一種壓縮性能良好的靜止圖像壓縮標準,適用于不同類型的靜止圖像壓縮,如自然圖像、遙感圖像、合成圖像、醫(yī)學(xué)圖像等,并在不同的應(yīng)用場合(如客戶/服務(wù)器模式、數(shù)字圖像檢索、實時傳輸?shù)?具有比JPEG更好的壓縮性能,因而具有廣闊的應(yīng)用前景。ADV212是目前基于JPEG2000算法所實現(xiàn)的主流編解碼芯片,但是其處理速度慢,并且不支持高分辨率圖像數(shù)據(jù)的處理。這極大限制了JPEG2000在高速、高分辨率等場合的應(yīng)用。因此,支持高速、高分辨處理的圖像解碼系統(tǒng)成為了國內(nèi)外研究的焦點。在JPEG2000解碼系統(tǒng)中,嵌入比特平面解碼是其核心組成部分,包括比特平面解碼和MQ解碼兩個核心模塊。由于嵌入比特平面解碼是高速解碼系統(tǒng)實現(xiàn)的瓶頸,因此本文針對該問題進行了研究,并針對其核心模塊MQ解碼器,提出了一種零延遲、高吞吐率的MQ算術(shù)解碼器結(jié)構(gòu),從而極大地提高了JPEG2000的解碼速度。為了進一步提高解碼器效率,本文對嵌入比特平面解碼進一步研究,提出了多路并行的實現(xiàn)方案,使其滿足實時處理的需求。本文主要研究內(nèi)容為MQ解碼器的結(jié)構(gòu)優(yōu)化以及Tier-1解碼的并行調(diào)度處理設(shè)計。文中首先簡要介紹了JPEG2000的核心算法,重點闡述了MQ編解碼算法和EBCOT碼塊編解碼原理。通過分析MQ解碼器效率的限制瓶頸,提出了一種MQ解碼器的結(jié)構(gòu)改進方案,并使用Xilinx公司的Vivado-HLS高級綜合工具,在Virtex-7 VC707硬件平臺上實現(xiàn)了一種零延遲、高吞吐率的MQ算術(shù)解碼器結(jié)構(gòu)。該解碼器能夠一個時鐘解碼一個判決,解碼器的吞吐率能達到102Mbps,所占資源不到1%。最后介紹了Tier-1解碼的并行調(diào)度方案和在ISE環(huán)境下的實現(xiàn)。該方案實現(xiàn)了多路Tier-1的并行調(diào)度處理。實驗結(jié)果表明,本文提出的MQ解碼器的優(yōu)化結(jié)構(gòu)和多路Tier-1并行調(diào)度處理有效地提高JPEG2000的解碼器效率,滿足入口速率為100Mbps壓縮圖像的實時解碼。
[Abstract]:JPEG2000 is a good compression performance of still image compression standard, suitable for different types of still image compression, such as natural images, remote sensing images, synthetic images, medical images, etc. And in different applications (such as client / server mode, digital image retrieval, real-time transmission, etc.) has better compression performance than JPEG, so it has a broad application prospect. ADV212 is a mainstream codec chip based on JPEG2000 algorithm. But its processing speed is slow, and it does not support the processing of high-resolution image data. This greatly limits the application of JPEG2000 in high-speed, high-resolution and other occasions. High-resolution image decoding system has become the focus of research at home and abroad. Embedded bit plane decoding is the core part of JPEG2000 decoding system. Because embedded bit plane decoding is the bottleneck of high-speed decoding system, this paper studies this problem, and aims at its core module MQ decoder, which includes two core modules: bit plane decoding and MQ decoding. An MQ arithmetic decoder architecture with zero delay and high throughput is proposed, which greatly improves the decoding speed of JPEG2000. In order to further improve the efficiency of the decoder, the embedded bit plane decoding is further studied in this paper. A multi-channel parallel implementation scheme is proposed to meet the requirements of real-time processing. This paper focuses on the structure optimization of MQ decoder and the design of parallel scheduling processing for Tier-1 decoding. Firstly, the core algorithm of JPEG2000 is introduced briefly. The MQ codec algorithm and the principle of EBCOT block coding and decoding are described in detail. By analyzing the bottleneck of the efficiency of MQ decoder, an improved scheme of MQ decoder structure is proposed, and the Vivado-HLS advanced synthesis tool of Xilinx company is used. An MQ arithmetic decoder structure with zero delay and high throughput is implemented on the Virtex-7 VC707 hardware platform. The throughput rate of the decoder can reach 102 Mbpss, which accounts for less than 1 resource. Finally, the parallel scheduling scheme of Tier-1 decoding and its implementation in ISE environment are introduced. The parallel scheduling processing of multi-channel Tier-1 is realized by this scheme. The experimental results show that, The optimized architecture of MQ decoder and multi-channel Tier-1 parallel scheduling process proposed in this paper can effectively improve the efficiency of JPEG2000 decoder and satisfy the real-time decoding of 100Mbps compressed images.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN764

【參考文獻】

相關(guān)期刊論文 前6條

1 邸志雄;史江義;劉凱;李云松;馬佩軍;郝躍;;多上下文MQ編碼器優(yōu)化與VLSI實現(xiàn)[J];電子學(xué)報;2013年05期

2 熊承義;陳方強;楊祖芳;;基于FPGA的MQ算術(shù)解碼器的設(shè)計與實現(xiàn)[J];中南民族大學(xué)學(xué)報(自然科學(xué)版);2009年01期

3 朱悅心;張靜;王勇;鄭南寧;;JPEG2000全通道并行EBCOT-Tier1編碼器結(jié)構(gòu)設(shè)計[J];電子與信息學(xué)報;2006年12期

4 楊海東;譚毅華;田金文;;一種適用于JPEG2000的流水線MQ編碼器設(shè)計[J];微計算機信息;2006年33期

5 魯則瑜,華林,朱柯,程君俠;JPEG2000高速MQ編解碼器的VLSI實現(xiàn)[J];復(fù)旦學(xué)報(自然科學(xué)版);2005年01期

6 劉凱,吳成柯,李云松,莊懷宇;比特平面并行的EBCOT編碼及其VLSI結(jié)構(gòu)[J];計算機學(xué)報;2004年07期

相關(guān)博士學(xué)位論文 前1條

1 黃全平;JPEG2000算法的VLSI實現(xiàn)及系統(tǒng)集成[D];復(fù)旦大學(xué);2005年

，

本文編號：1500933