本文關(guān)鍵詞： 多FPGA SoC 芯片驗(yàn)證 邏輯劃分　出處：《大連理工大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著SoC和IP核技術(shù)的推廣,邏輯驗(yàn)證已成為芯片設(shè)計領(lǐng)域的一個主要難題。許多案例中,芯片的邏輯驗(yàn)證團(tuán)隊規(guī)模甚至超過邏輯設(shè)計團(tuán)隊。軟件仿真技術(shù)作為目前最常見的邏輯驗(yàn)證方法,其靈活性值得肯定,但具有驗(yàn)證規(guī)模小、效率低等致命缺陷。FPGA硬件驗(yàn)證技術(shù)可提供優(yōu)良的驗(yàn)證準(zhǔn)確性和高效性,多FPGA驗(yàn)證技術(shù)可實(shí)現(xiàn)對大規(guī)模芯片的邏輯驗(yàn)證。本論文致力于運(yùn)用多PFGA驗(yàn)證平臺搭建芯片設(shè)計的原型系統(tǒng),以實(shí)現(xiàn)大規(guī)模SoC芯片的邏輯驗(yàn)證。通過敘述SoC和IP核復(fù)用技術(shù)為芯片驗(yàn)證帶來規(guī)模上挑戰(zhàn)和機(jī)遇,展開了芯片驗(yàn)證方法的敘述,討論軟硬件方法存在的問題。我們重點(diǎn)介紹了FPGA的驗(yàn)證方法,并致力于解決多PFGA原型驗(yàn)證系統(tǒng)中存在的兩大關(guān)鍵問題：SoC邏輯劃分和多FPGA芯片互連。本文經(jīng)過邏輯模塊樹提取和資源需求分析后,設(shè)計了邏輯劃分算法,算法的時間復(fù)雜度為O(n)。邏輯劃分算法實(shí)現(xiàn)中,運(yùn)用現(xiàn)有EDA軟件進(jìn)行資源信息提取,以XML文件進(jìn)行邏輯模塊樹的記錄,最終依據(jù)算法結(jié)果指導(dǎo)RTL代碼修改。多FPGA互連問題則PCIe,總線架構(gòu),以RocketIO進(jìn)行實(shí)現(xiàn)。為確保算法設(shè)計有效,本文在自研的多FPGA原型驗(yàn)證平臺上,使用RSA硬件加密算法核和Leon3 SoC IP核進(jìn)行了正確性、高效性、統(tǒng)計實(shí)驗(yàn)。實(shí)驗(yàn)結(jié)果表明：多FPGA驗(yàn)證平臺設(shè)計合理；SoC邏輯劃分算法正確且高效；多FPGA互連結(jié)構(gòu)可擴(kuò)展。論文工作有一定的創(chuàng)新性和應(yīng)用價值。
[Abstract]:With the spread of SoC and IP technologies, logic verification has become a major challenge in the field of chip design. The size of the logical verification team is even larger than that of the logical design team. As the most common logic verification method at present, the flexibility of the software simulation technology is commendable, but it has a small scale of verification. Low efficiency and other fatal defects. FPGA hardware verification technology can provide excellent verification accuracy and efficiency, Multiple FPGA verification technology can realize the logical verification of large scale chips. This thesis is devoted to building a prototype system of chip design using multiple PFGA verification platform. In order to realize the logical verification of large scale SoC chip, the paper describes the challenges and opportunities brought by SoC and IP core reuse technology to the scale of chip verification, and presents the method of chip verification. The problems of software and hardware methods are discussed. We mainly introduce the verification method of FPGA. And it is devoted to solve the two key problems in the prototype verification system:: SoC logic partition and multi-#en1# chip interconnection. After the logic module tree extraction and resource requirement analysis, the logic partition algorithm is designed in this paper. In the realization of logic partition algorithm, the existing EDA software is used to extract the resource information, and the XML file is used to record the logic module tree. Finally, according to the result of the algorithm, the RTL code is modified. In order to ensure the effective design of the algorithm, the multi-#en1# interconnection problem is implemented on the multi-#en3# prototype verification platform, which is based on the bus architecture and implemented by RocketIO. The RSA hardware encryption algorithm core and the Leon3 SoC IP core are used to carry out the correctness, high efficiency and statistical experiment. The experimental results show that the multi-#en3# verification platform is designed reasonably and the algorithm is correct and efficient. Multi-FPGA interconnection structure is extensible. The work of this paper has some innovation and application value.
【學(xué)位授予單位】：大連理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN47

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本文編號：1494969