發(fā)布時間：2018-02-03 14:29

  本文關(guān)鍵詞： SoC 低功耗 FPGA　出處：《西安電子科技大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著電子技術(shù)的發(fā)展,越來越多的智能設(shè)備出現(xiàn)在人們的生活中。物聯(lián)網(wǎng)的概念提出將這些智能設(shè)備相互連接,從而更好地提高人們的生活品質(zhì),這對無線通信芯片提出了需求。同時智能設(shè)備也向著小型化和集成化的方向發(fā)展,對低功耗提出了一定要求。本文基于以上背景設(shè)計(jì)了一款低功耗藍(lán)牙SoC芯片XD1336,并對其進(jìn)行了仿真驗(yàn)證與FPGA驗(yàn)證。文章簡要介紹了低功耗藍(lán)牙SoC的發(fā)展背景和數(shù)字系統(tǒng)的設(shè)計(jì)流程。下面就流程中設(shè)計(jì)與驗(yàn)證兩個步驟,結(jié)合低功耗藍(lán)牙SoC進(jìn)行了闡述。論文首先對整個芯片的架構(gòu)進(jìn)行了描述,簡要介紹了系統(tǒng)各個模塊的功能。之后就筆者在項(xiàng)目中參與設(shè)計(jì)和驗(yàn)證的工作進(jìn)行了詳細(xì)介紹。包括調(diào)制解調(diào)模塊的原理以及數(shù)字實(shí)現(xiàn)的具體方案、RF控制模塊的設(shè)計(jì)、系統(tǒng)的低功耗模式以及實(shí)現(xiàn)的具體技術(shù)細(xì)節(jié)。其中低功耗模式介紹了Sleep、Deep Sleep和Shutdown三種模式,并分析了他們的應(yīng)用環(huán)境。實(shí)現(xiàn)低功耗的具體細(xì)節(jié)涉及了門控時鐘、隔離單元以及CPF文件的應(yīng)用。接下來對上述部分進(jìn)行了仿真,以驗(yàn)證設(shè)計(jì)是否符合要求。這一部分使用計(jì)算機(jī)仿真軟件,對數(shù)字邏輯進(jìn)行仿真并產(chǎn)生波形,并觀察信號波形來確認(rèn)設(shè)計(jì)是否實(shí)現(xiàn)了預(yù)期的功能。這一部分首先介紹了仿真平臺的搭建,之后依次分析了調(diào)制解調(diào)模塊、RF控制模塊以及低功耗模式的仿真波形。從仿真波形可以看出,調(diào)制解調(diào)模塊可以正常地處理信號,并可以與測試模型通信;RF控制模塊信號的時序與設(shè)計(jì)要求一致;低功耗模式下相關(guān)的信號跳變正常,說明系統(tǒng)進(jìn)入了低功耗模式。這一部分通過仿真驗(yàn)證,得出了系統(tǒng)功能符合設(shè)計(jì)要求的結(jié)論。然后介紹了利用FPGA補(bǔ)充驗(yàn)證系統(tǒng)功能的工作。此處首先介紹了FPGA與CPLD的差別,闡明了選擇FPGA作為驗(yàn)證平臺的理由。接著對搭建的FPGA驗(yàn)證平臺做了簡要描述。之后提出了進(jìn)行FPGA驗(yàn)證平臺與PTS Dongle通信測試,同時通過內(nèi)嵌式分析邏輯分析儀抓取的重要信號的波形的驗(yàn)證方案。經(jīng)過測試驗(yàn)證,FPGA驗(yàn)證平臺可以和PTS Dongle正常通信,邏輯分析儀抓取的信號也與仿真中一致,說明設(shè)計(jì)通過了FPGA驗(yàn)證,系統(tǒng)功能正常無誤。最后對全文進(jìn)行了回顧與總結(jié)。指出了本人工作中仍存在的不足之處,并對未來做出了展望。
[Abstract]:With the development of electronic technology, more and more intelligent devices appear in people's life. The concept of Internet of things proposes to connect these intelligent devices to each other, so as to improve people's quality of life better. At the same time, intelligent devices are developing towards miniaturization and integration. In this paper, a low power Bluetooth SoC chip XD1336 is designed based on the above background. The paper introduces the development background of low-power Bluetooth SoC and the design process of digital system. The following two steps are the design and verification of the process. In this paper, the low power Bluetooth SoC is introduced. Firstly, the architecture of the whole chip is described. After a brief introduction of the functions of each module of the system, the author in the project involved in the design and verification of the work is described in detail, including the principle of modulation and demodulation module and digital implementation of the specific scheme. The design of RF control module, the low power mode of the system and the technical details of its implementation. The low power mode introduces three modes of deep Sleep and Shutdown. And analyzed their application environment. The implementation of low-power details involved the application of gated clock, isolation unit and CPF file. In order to verify whether the design meets the requirements. This part uses computer simulation software to simulate the digital logic and generate waveform. And observe the signal waveform to confirm whether the design has achieved the expected function. This part first introduces the construction of the simulation platform, and then analyzes the modulation and demodulation module in turn. RF control module and simulation waveform of low power mode. From the simulation waveform, it can be seen that the modulation and demodulation module can process the signal normally, and can communicate with the test model; RF control module signal timing and design requirements are consistent; The related signal jump is normal in low-power mode, which indicates that the system has entered low-power mode. This part is verified by simulation. A conclusion is drawn that the function of the system meets the design requirements. Then the work of using FPGA to supplement and verify the system function is introduced. The difference between FPGA and CPLD is introduced here first. The reason for choosing FPGA as the verification platform is explained. Then the FPGA verification platform is briefly described. Then, the FPGA verification platform and PTS are proposed. Dongle communication test. At the same time, the verification scheme of the waveform of the important signal captured by the embedded analysis logic analyzer is adopted. After testing, the verification platform can communicate with PTS Dongle normally. The signal captured by the logic analyzer is also consistent with the simulation, which shows that the design has passed the FPGA verification. The function of the system is normal and correct. Finally, the paper reviews and summarizes the full text, points out the shortcomings of my work, and makes a prospect for the future.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN402

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本文編號：1487604