本文關(guān)鍵詞： MOSFET 小信號(hào)建模 參數(shù)提取 靈敏度分析 蒙特卡洛方法　出處：《華東師范大學(xué)》2017年碩士論文　論文類(lèi)型：學(xué)位論文

【摘要】：MOSFET(金屬氧化物半導(dǎo)體場(chǎng)效應(yīng)晶體管)以其特有的功耗低、工藝成熟、集成度高以及與模擬電路的耦合性良好等優(yōu)勢(shì)在射頻集成電路中充當(dāng)著不可或缺的角色。在設(shè)計(jì)研制電路時(shí),為了縮短研發(fā)時(shí)間和降低研發(fā)成本,利用器件模型代替實(shí)物以模擬電路性能是個(gè)很有效的途徑。同時(shí)電路的設(shè)計(jì)與仿真必然要用到計(jì)算機(jī)輔助軟件,軟件中所使用的內(nèi)嵌器件模型的準(zhǔn)確度也很大程度地影響著電路設(shè)計(jì)的結(jié)果。本文的研究工作主要圍繞90納米MOSFET器件等效電路模型的建立展開(kāi),深入研究了 MOSFET器件的小信號(hào)模型及其相關(guān)理論,回顧了集成電路和半導(dǎo)體器件的發(fā)展,在當(dāng)前MOSFET模型的理論基礎(chǔ)上,提出了對(duì)MOSFET器件建模技術(shù)的改良提高。本文的主要研究工作包括:1)對(duì)MOSFET器件建模流程和小信號(hào)模型參數(shù)的提取流程進(jìn)行了闡述;2)在對(duì)MOSFET器件去嵌過(guò)程中,提出了改進(jìn)創(chuàng)新的測(cè)試結(jié)構(gòu)短路模型,相應(yīng)的開(kāi)路短路去嵌過(guò)程相較于傳統(tǒng)去嵌方法也有所不同。采用新的去嵌方法提取出的創(chuàng)新型測(cè)試結(jié)構(gòu)短路模型的精度比傳統(tǒng)模型有了很大的改善和提高。并將其應(yīng)用于4×0.6μm(柵指數(shù)×柵寬)、柵長(zhǎng)為90nm并且由18個(gè)元胞構(gòu)成的MOSFET器件建模上,獲得的器件模型在準(zhǔn)確度上較之傳統(tǒng)模型也有所提高;3)在器件單胞模型的基礎(chǔ)上,提出了符合器件真實(shí)物理結(jié)構(gòu)的多胞模型,并應(yīng)用于8×0.6μm(柵指數(shù)×柵寬)、柵長(zhǎng)為90nm、由12個(gè)元胞構(gòu)成的MOSFET器件上,獲得的等效電路模型更加貼近實(shí)驗(yàn)測(cè)量數(shù)據(jù)結(jié)果,其模型能夠更加準(zhǔn)確地預(yù)測(cè)MOSFET的行為;4)以單胞模型為研究對(duì)象,分析電路模型本征部分中各個(gè)元件的靈敏度。應(yīng)用蒙特卡洛方法對(duì)各個(gè)元件靈敏度進(jìn)行仿真驗(yàn)證,證明元件靈敏度的準(zhǔn)確性,并從敏感度方面考察電路模型的穩(wěn)定性。
[Abstract]:MOSFET (Metal oxide Semiconductor Field effect Transistor) has low power consumption and mature technology. The advantages of high integration and good coupling with analog circuits play an indispensable role in RF integrated circuits. In order to shorten the R & D time and reduce the R & D costs in the design and development of circuits. It is an effective way to use the device model instead of the physical object to simulate the circuit performance. At the same time, the design and simulation of the circuit must use computer aided software. The accuracy of embedded device model used in software also greatly affects the results of circuit design. The research work in this paper mainly revolves around the establishment of equivalent circuit model of 90 nanometer-sized MOSFET devices. The small signal model and its related theories of MOSFET devices are studied in depth. The development of integrated circuits and semiconductor devices is reviewed. Based on the current MOSFET model theory. The main research work in this paper includes: (1) the modeling process of MOSFET device and the extraction process of small signal model parameters are described. 2) in the process of removing MOSFET devices, an improved and innovative short circuit model of test structure is proposed. The corresponding open-circuit short-circuit de-embedding process is also different from the traditional de-embedding method. The precision of the innovative test structure short-circuit model extracted by the new de-embedding method has been greatly improved and improved compared with the traditional model. It was applied to 4 脳 0.6 渭 m (. Gate index 脳 gate width). When the gate length is 90 nm and the MOSFET device is composed of 18 cells, the accuracy of the device model obtained is also improved compared with the traditional model. 3) based on the unit cell model of the device, a polycell model which accords with the real physical structure of the device is proposed and applied to 8 脳 0.6 渭 m (gate index 脳 gate width, gate length 90 nm). On MOSFET devices composed of 12 cells, the equivalent circuit model obtained is closer to the experimental data, and the model can predict the behavior of MOSFET more accurately. 4) taking the unit cell model as the research object, the sensitivity of each component in the intrinsic part of the circuit model is analyzed, and the sensitivity of each component is verified by Monte Carlo method, which proves the accuracy of the element sensitivity. The stability of the circuit model is investigated from the sensitivity aspect.
【學(xué)位授予單位】：華東師范大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類(lèi)號(hào)】：TN386

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