發(fā)布時(shí)間：2018-01-29 05:03

  本文關(guān)鍵詞： 鎖相環(huán) 環(huán)路帶寬 捕獲時(shí)間 相位噪聲 最佳環(huán)路帶寬　出處：《中國(guó)科學(xué)院研究生院(空間科學(xué)與應(yīng)用研究中心)》2015年碩士論文　論文類(lèi)型：學(xué)位論文

【摘要】：隨著科學(xué)技術(shù)的發(fā)展與進(jìn)步,鎖相環(huán)作為一個(gè)相位自動(dòng)反饋系統(tǒng),以其窄帶跟蹤、控制無(wú)頻差、低門(mén)限、抗干擾能力強(qiáng)以及易于集成化等諸多優(yōu)點(diǎn),在電子相關(guān)的多個(gè)領(lǐng)域得到了極其廣泛的應(yīng)用。在鎖相環(huán)的設(shè)計(jì)過(guò)程中,環(huán)路帶寬的選擇是整個(gè)設(shè)計(jì)成功與否的重要一環(huán)。一方面,環(huán)路帶寬的選取會(huì)影響環(huán)路捕獲帶和捕獲時(shí)間,即環(huán)路的捕獲性能;另一方面,環(huán)路輸出相位噪聲的大小不僅與環(huán)路各器件噪聲特性有關(guān),其在很大程度上依賴(lài)于環(huán)路帶寬的選取。因此,本文針對(duì)環(huán)路帶寬與環(huán)路捕獲性能的關(guān)系、環(huán)路帶寬對(duì)環(huán)路輸出相位噪聲的影響進(jìn)行了深入的探討與研究。第一章,著重介紹鎖相技術(shù)發(fā)展歷史、應(yīng)用領(lǐng)域及發(fā)展現(xiàn)狀;第二章,從鎖相環(huán)基本原理入手,從理論上分析了簡(jiǎn)單二階鎖相環(huán)環(huán)路帶寬和環(huán)路捕獲性能的關(guān)系以及環(huán)路輸出相位噪聲模型;第三章,利用ADS電路仿真軟件,搭建基于不同類(lèi)型環(huán)路濾波器的鎖相環(huán)電路模型,并對(duì)其分別進(jìn)行時(shí)域仿真和頻域仿真來(lái)驗(yàn)證理論分析;第四章,基于PE3236鎖相環(huán)PLL芯片,完成了一款高性能鎖相頻率合成電路的設(shè)計(jì);第五章,對(duì)鎖相頻率合成電路進(jìn)行調(diào)試和測(cè)試,通過(guò)調(diào)節(jié)電路參數(shù)改變環(huán)路帶寬,測(cè)試不同環(huán)路帶寬條件下環(huán)路捕獲時(shí)間和輸出相位噪聲,測(cè)試結(jié)果與理論分析基本吻合。
[Abstract]:With the development and progress of science and technology, PLL, as a phase automatic feedback system, has many advantages, such as narrow band tracking, no frequency difference control, low threshold, strong anti-jamming ability and easy integration. In the design process of PLL, the choice of loop bandwidth is an important link for the success of the whole design. The selection of loop bandwidth will affect the capture band and time of the loop, that is, the performance of the loop. On the other hand, the output phase noise of the loop is not only related to the noise characteristics of the loop devices, but also depends on the selection of the loop bandwidth to a great extent. In this paper, the relationship between loop bandwidth and the performance of loop acquisition is discussed. The influence of loop bandwidth on loop output phase noise is discussed. Chapter 1 focuses on the history of phase-locked technology. Application field and development status; In the second chapter, starting with the basic principle of PLL, the relationship between the bandwidth of the simple second-order PLL loop and the performance of the loop acquisition and the output phase noise model of the loop are analyzed theoretically. In chapter 3, using the ADS circuit simulation software, the phase-locked loop circuit model based on different types of loop filter is built, and the time domain simulation and frequency domain simulation are carried out to verify the theoretical analysis. In chapter 4th, based on PE3236 PLL PLL chip, a high performance PLL frequency synthesizer is designed. In Chapter 5th, the phase-locked frequency synthesizer is debugged and tested. By adjusting the circuit parameters, the loop bandwidth is changed to test the loop acquisition time and the output phase noise under different loop bandwidth conditions. The test results are in good agreement with the theoretical analysis.
【學(xué)位授予單位】：中國(guó)科學(xué)院研究生院(空間科學(xué)與應(yīng)用研究中心)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN74

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相關(guān)期刊論文 前1條

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本文編號(hào)：1472601