發(fā)布時(shí)間：2018-01-28 12:58

  本文關(guān)鍵詞： DI結(jié)構(gòu) 介電常數(shù) 電流模型 閾值電壓 SCE　出處：《安徽大學(xué)》2015年碩士論文　論文類(lèi)型：學(xué)位論文

【摘要】：隨著信息技術(shù)發(fā)展,MOSFET尺寸進(jìn)一步減小,使得對(duì)集成電路的密集度進(jìn)一步提升。器件尺寸減小能有效地提高集成度、大信息量存儲(chǔ)等要求,但是伴隨而出的各種不良性能卻越來(lái)越多。通過(guò)各種新型結(jié)構(gòu)設(shè)計(jì)和新的工藝技術(shù)能有效降低上述不良性能,目前解決的辦法主要有三種途徑：一是在多研究一些新的理論模型；二是優(yōu)化設(shè)計(jì),尋找有效設(shè)計(jì)辦法來(lái)提升MOSFET性能；三是在工藝上尋找新半導(dǎo)體材料、新型器件結(jié)構(gòu)等。本文從上述第三點(diǎn)出發(fā),構(gòu)造了一個(gè)新的器件模型,對(duì)其相關(guān)特性進(jìn)行了模型建立與仿真,并對(duì)四種DI層結(jié)構(gòu)隨兩種介電材料介電常數(shù)(ε)差值變化的相關(guān)特性進(jìn)行了分析與討論。本文在雙柵DG (Double Gate)勺框架上,將柵絕緣層(Gate Insulator, GI)材料用兩個(gè)ε值不同材料替換構(gòu)成一個(gè)雙重柵極絕緣層結(jié)構(gòu)(Dual Insulator, DI),構(gòu)造了一個(gè)新的DIDG MOSFET,并以DI層兩種介質(zhì)材料ε差值的不同,建立了四種DIDG器件。研究發(fā)現(xiàn),DIDG器件在溝道區(qū)域內(nèi)有兩個(gè)電場(chǎng)最大值而普通DG器件在溝道區(qū)域內(nèi)只有一個(gè)電場(chǎng)最大值；這個(gè)增加的電場(chǎng)會(huì)使得DI器件電場(chǎng)平均值大于普通DG器件電場(chǎng)平均值；DI結(jié)構(gòu)溝道內(nèi)電子平均速度大于普通DG結(jié)構(gòu)電子平均速度,然而DI器件漏端電場(chǎng)卻比DG器件漏端電場(chǎng)要小,因此在熱載流子效應(yīng)(HCE)抑制方面DI器件更有優(yōu)勢(shì)。同時(shí)仿真ID-VDS特性和ID-VGS特性發(fā)現(xiàn),DI器件比普通DG器件,具有更高的漏電流及較好負(fù)載力、電流在飽和區(qū)的飽和度更好,在HCE抑制方面更有優(yōu)勢(shì)。伴隨著DI層兩種材料ε差值的增大,器件溝道電場(chǎng)越高且分布更均一、ID-vDS特性和ID-VGS特性更加優(yōu)越、漏電流越高及負(fù)載力越好、對(duì)SCE抑制作用更強(qiáng)、器件的閾值電壓(Vth)越大、亞閾值斜率(S)越小、器件開(kāi)關(guān)性能越好、電子平均速度更高、電流密度更大。依據(jù)DI層兩種材料ε差值的仿真分析,對(duì)DI層材料長(zhǎng)度進(jìn)行不同配比率優(yōu)化設(shè)計(jì),設(shè)計(jì)發(fā)現(xiàn),隨著配比率降低(3：2→1：1→2：3),溝道電場(chǎng)越大且更均-漏電流更高且負(fù)載力越強(qiáng)、漏電流飽和度越好且對(duì)SCE抑制更好好、電子平均速度更大、電流密度更大。同時(shí)通過(guò)不同的配比率仿真發(fā)現(xiàn),隨著配比率降低(3：2→1：1→2：3),器件的Vth值越大,因此可以通過(guò)不同配比率進(jìn)行Vth值調(diào)控。本文對(duì)四種DI結(jié)構(gòu)硅體中最低電勢(shì)點(diǎn)電勢(shì)進(jìn)行修正,建立了最小電勢(shì)點(diǎn)電勢(shì)模型,同時(shí)在電勢(shì)模型前提下,構(gòu)造了閾值電壓(VT)模型和亞閾值電流(ID)模型。通過(guò)MEDICI對(duì)模型進(jìn)行了仿真驗(yàn)證,結(jié)果趨勢(shì)一致,吻合度良好。
[Abstract]:With the development of information technology, the size of MOSFET is further reduced, which makes the density of integrated circuits increase further. The reduction of device size can effectively improve the integration, large amount of information storage and other requirements. However, there are more and more bad properties, which can be effectively reduced by a variety of new structural design and new technology. At present, there are three main ways to solve the problem: first, we are studying more new theoretical models; The second is to optimize the design to find effective design methods to improve the performance of MOSFET; The third is to find new semiconductor materials and new device structures in the process. In this paper, a new device model is constructed from the third point above, and its related characteristics are modeled and simulated. The correlation characteristics of four kinds of DI layer structures with the difference of dielectric constant (蔚) of two kinds of dielectric materials are analyzed and discussed. The gate insulator (GI) material is replaced by two different 蔚 values to form a dual gate insulator (dual Insulator) structure. A new DIDG MOSFET is constructed, and four kinds of DIDG devices are built according to the difference of 蔚 between two kinds of dielectric materials in DI layer. The DIDG device has two maximum electric fields in the channel region, while the ordinary DG device has only one maximum electric field in the channel region. The increasing electric field will make the average electric field of DI device larger than the average electric field of ordinary DG device. The average electron velocity in the channel of DI structure is higher than that in ordinary DG structure, but the leakage electric field of DI device is smaller than that of DG device. Therefore, DI devices have more advantages in the suppression of hot carrier effect (HCE). At the same time, the simulation of ID-VDS and ID-VGS characteristics shows that DI devices are better than ordinary DG devices. With higher leakage current and better load force, the saturation of the current in the saturation region is better, and the HCE suppression is more advantageous, with the increase of 蔚 difference between the two kinds of materials in DI layer. The higher the channel electric field and the more uniform distribution of ID-vDS and ID-VGS characteristics, the better the leakage current and load force, the stronger the inhibition to SCE. The larger the threshold voltage is, the smaller the sub-threshold slope is, the better the switch performance, the higher the average electron speed and the greater the current density. The simulation analysis is based on the 蔚 difference between two kinds of materials in DI layer. The optimum design of different ratio of DI layer material length was carried out. It was found that with the ratio ratio decreasing, the ratio decreased by 3: 2. 鈫，

本文編號(hào)：1470829