本文關(guān)鍵詞： 專用集成電路(ASIC) 超低功耗 電壓基準(zhǔn)源 亞閾值 電源電壓抑制比(PSRR) 共源共柵電流鏡　出處：《半導(dǎo)體技術(shù)》2016年04期 　論文類型：期刊論文

【摘要】：介紹了一種超低功耗、無片上電阻、無雙極型晶體管(BJT)的基于亞閾值CMOS特性的基準(zhǔn)電壓源,該帶隙基準(zhǔn)源主要用于低功耗型專用集成電路(ASIC)。采用Oguey電流源結(jié)構(gòu)來減小靜態(tài)電流,以降低功耗。通過使用工作在線性區(qū)的MOS管代替?zhèn)鹘y(tǒng)結(jié)構(gòu)中的電阻消除遷移率和電流的溫度影響,同時(shí)減小芯片面積;采用共源共柵電流鏡以降低電源電壓抑制比和電壓調(diào)整率。電路基于SMIC 0.18μm CMOS工藝進(jìn)行仿真。仿真結(jié)果表明,在-45~130℃內(nèi),溫漂系數(shù)為29.1×10-6/℃,電源電壓范圍為0.8~3.3 V時(shí),電壓調(diào)整率為0.056%,在100 Hz時(shí),電源電壓抑制比為-53 d B。電路功耗僅為235 n W,芯片面積為0.01 mm2。
[Abstract]:An ultra-low power, no on-chip resistor, no bipolar transistor (BJT) based reference voltage source based on sub-threshold CMOS characteristics is introduced. The bandgap reference is mainly used in low power ASIC. The Oguey current source structure is used to reduce the static current. In order to reduce power consumption, the temperature effect of mobility and current is eliminated by replacing the resistance in the traditional structure with the MOS transistor operating in the linear region, and the chip area is reduced. The circuit is simulated based on SMIC 0.18 渭 m CMOS process. The simulation results show that the circuit can reduce the voltage rejection ratio and voltage adjustment rate. When the temperature drift coefficient is 29.1 脳 10 ~ (-6) / 鈩，

本文編號(hào)：1452478