本文關(guān)鍵詞： 規(guī)整電路 位片 數(shù)據(jù)通路 交叉開關(guān) 半自動(dòng)　出處：《國防科學(xué)技術(shù)大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：EDA自動(dòng)化工具的不斷進(jìn)步,大大縮短了集成電路的設(shè)計(jì)周期,其布局與優(yōu)化算法對(duì)隨機(jī)邏輯功能塊具有很好的物理實(shí)現(xiàn)與優(yōu)化效果,但對(duì)于復(fù)雜性較高的規(guī)整結(jié)構(gòu),EDA工具不能高效的利用電路內(nèi)部規(guī)整性去實(shí)現(xiàn)高性能設(shè)計(jì)的時(shí)序收斂。針對(duì)上述問題,本文總結(jié)和優(yōu)化了對(duì)規(guī)整電路物理設(shè)計(jì)具有良好優(yōu)化效果的半自動(dòng)物理實(shí)現(xiàn)方法。半自動(dòng)物理實(shí)現(xiàn)方法的優(yōu)勢(shì)在于可以借助腳本來快速實(shí)現(xiàn)規(guī)整電路的手工布局,利用布局的規(guī)整性來引導(dǎo)工具自動(dòng)布線,提高規(guī)整電路的性能。首先,從RTL代碼中挖掘出電路內(nèi)部存在的規(guī)整性,用能夠體現(xiàn)規(guī)整性的最小可重復(fù)單元組合成規(guī)整電路的電路圖,以手工搭建電路的方式代替工具自動(dòng)綜合,提取包含電路規(guī)整信息的門級(jí)網(wǎng)表。其次,根據(jù)電路的布圖規(guī)劃約束,確定最小可重復(fù)單元的布局形狀與在物理視圖中的絕對(duì)位置,精確計(jì)算出可重復(fù)單元間的相對(duì)間距,借助腳本將最小可重復(fù)單元的手工部局信息復(fù)制到其它可重復(fù)單元之中,快速完成規(guī)整單元的手工布局。最后,讓規(guī)整的布局來引導(dǎo)工具自動(dòng)布線,高效地實(shí)現(xiàn)電路的物理設(shè)計(jì)。根據(jù)電路結(jié)構(gòu)的不同可以將規(guī)整結(jié)構(gòu)分為位片式一維規(guī)整結(jié)構(gòu)和二維陣列規(guī)整結(jié)構(gòu)。數(shù)據(jù)通路常常組織成位片式結(jié)構(gòu)。位片式結(jié)構(gòu)中所有數(shù)據(jù)位的結(jié)構(gòu)完全相同或相似,設(shè)計(jì)者只需實(shí)現(xiàn)一位的手工布局,然后將該位的物理信息重復(fù)調(diào)用,快速構(gòu)建出整給數(shù)據(jù)通路的手工布局。本文以數(shù)據(jù)通路中地址部件為實(shí)驗(yàn)載體,利用半自動(dòng)物理實(shí)現(xiàn)方法將數(shù)據(jù)通路中的規(guī)整性運(yùn)用于物理實(shí)現(xiàn),使得地址部件的功耗降低了3.62%,延時(shí)最大減少10.34%。二維陣列規(guī)整結(jié)構(gòu)通常存在于大量數(shù)據(jù)交換通路之中。交叉開關(guān)網(wǎng)絡(luò)需要譯碼陣列與選擇陣列的協(xié)同合作才能完成交叉開關(guān)的功能,具有典型的二維規(guī)整陣列。EDA自動(dòng)布局算法不能很好地處理復(fù)雜的邏輯陣列。半自動(dòng)物理實(shí)現(xiàn)方式可以提取二維陣列中的最小可重復(fù)單元,然后以它的布局信息為模板,借助腳本快速實(shí)現(xiàn)整個(gè)二維陣列規(guī)整的手工布局。本文選取具有規(guī)整結(jié)構(gòu)的交叉開關(guān)網(wǎng)絡(luò)作為二維陣列規(guī)整結(jié)構(gòu)的實(shí)現(xiàn)載體,將這種陣列規(guī)整性充分地運(yùn)用到物理實(shí)現(xiàn)過程中,使功耗降低了26.37%,延時(shí)最大減少了25.1%。在高性能芯片設(shè)計(jì)過程中,設(shè)計(jì)者可以應(yīng)用這種方法優(yōu)化芯片內(nèi)的規(guī)整電路,以協(xié)助芯片整體的優(yōu)化工作。
[Abstract]:With the continuous progress of EDA automation tools, the design cycle of integrated circuits is greatly shortened. The layout and optimization algorithms have good physical realization and optimization effect for random logic function blocks. However, EDA tools with high complexity can not efficiently utilize the internal regularity of the circuit to achieve the timing convergence of high performance design. This paper summarizes and optimizes the semi-automatic physical realization method which has good optimization effect on the physical design of regular circuit. The advantage of semi-automatic physical realization method is that the manual layout of regular circuit can be realized quickly by means of script. . Using the layout regularity to guide the tool automatic routing, improve the performance of the structured circuit. Firstly, the internal regularity of the circuit is mined from the RTL code. The circuit diagram is composed of the least repeatable unit which can reflect the regularity of the circuit. Instead of the tool, the circuit is automatically synthesized by manual construction, and the gate network table which contains the information of circuit regularity is extracted. Secondly. According to the layout planning constraints of the circuit, the layout shape of the minimum repeatable cell and the absolute position in the physical view are determined, and the relative distance between the repeatable elements is calculated accurately. With the help of the script, the manual information of the smallest repeatable unit is copied to other repeatable units, and the manual layout of the regular unit is completed quickly. Finally, let the regular layout to guide the tool automatic routing. The physical design of the circuit can be realized efficiently. According to the different circuit structure, the structured structure can be divided into one dimensional structure and two dimensional array structure. The data path is often organized into a bit-chip structure. The structure of all data bits in the. The designer only need to realize the manual layout of one bit, then repeat the physical information of the bit, and quickly construct the manual layout of the integrated data path. In this paper, the address part of the data path is used as the experimental carrier. By using semi-automatic physical implementation method, the regularity in the data path is applied to the physical implementation, and the power consumption of the address component is reduced by 3.62%. The maximum delay is reduced by 10.34. The two-dimensional array regularization structure usually exists in a large number of data exchange paths. The cross-switch network needs the cooperative cooperation of decoding array and selecting array to complete the function of crossover switch. . A typical two-dimensional structured array. EDA automatic layout algorithm can not deal with complex logical arrays. Semi-automatic physical implementation can extract the smallest repeatable elements in two-dimensional arrays. Then the layout information is used as template, and the manual layout of the whole two-dimensional array is realized quickly by means of script. In this paper, the cross-switch network with regular structure is selected as the implementation carrier of two-dimensional array warping structure. The array regularity is fully applied to the physical implementation process, the power consumption is reduced by 26.37, the delay is reduced by 25.1. in the process of high performance chip design. This method can be used to optimize the structured circuits in the chip to assist the overall optimization of the chip.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN40

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