本文關(guān)鍵詞： 功能覆蓋率 OVM System Verilog 驗(yàn)證平臺(tái) 自動(dòng)化　出處：《西安電子科技大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：本論文的研究重點(diǎn)是數(shù)字集成電路設(shè)計(jì)中的驗(yàn)證技術(shù)。隨著集成電路技術(shù)的高速發(fā)展,芯片設(shè)計(jì)的規(guī)模越來(lái)越大,功能越來(lái)越復(fù)雜,導(dǎo)致在電路設(shè)計(jì)階段設(shè)計(jì)缺陷出現(xiàn)的可能性越來(lái)越高,于是對(duì)驗(yàn)證的要求越來(lái)越高。并且現(xiàn)在芯片的應(yīng)用領(lǐng)域越來(lái)越廣泛,對(duì)設(shè)計(jì)安全性的要求也越來(lái)越高,設(shè)計(jì)漏洞的出現(xiàn)可能會(huì)造成非常嚴(yán)重的后果,驗(yàn)證的充分性也顯得尤為重要。市場(chǎng)對(duì)芯片產(chǎn)品更新?lián)Q代的要求也越來(lái)越快,而在大規(guī)模集成電路開發(fā)的前端設(shè)計(jì)流程中,驗(yàn)證工作已經(jīng)占到了總工作量的百分之七十左右。如何在保證驗(yàn)證充分性的前提下,提高驗(yàn)證效率成為集成電路設(shè)計(jì)開發(fā)中的瓶頸。找到高效、可行的驗(yàn)證方法非常重要。本文在詳細(xì)對(duì)比分析了傳統(tǒng)的定向驗(yàn)證方法、帶約束的隨機(jī)化激勵(lì)驗(yàn)證方法以及基于覆蓋率驅(qū)動(dòng)的驗(yàn)證方法的基礎(chǔ)上,針對(duì)當(dāng)前驗(yàn)證工作面臨的完備性、可重用性、可靠性和效率等方面的挑戰(zhàn),結(jié)合基于功能覆蓋率驅(qū)動(dòng)的驗(yàn)證方法和OVM驗(yàn)證方法學(xué),設(shè)計(jì)實(shí)現(xiàn)了功能覆蓋率驅(qū)動(dòng)器組件。論文所設(shè)計(jì)的功能覆蓋率驅(qū)動(dòng)組件實(shí)現(xiàn)了功能覆蓋率的動(dòng)態(tài)自動(dòng)化分析,可根據(jù)分析結(jié)果指導(dǎo)驗(yàn)證平臺(tái)中的序列產(chǎn)生器產(chǎn)生有針對(duì)性的測(cè)試激勵(lì),并易于集成到OVM架構(gòu)的驗(yàn)證環(huán)境中。該模塊基于功能覆蓋率驅(qū)動(dòng)的驗(yàn)證方法,實(shí)現(xiàn)了驗(yàn)證的完備性;基于OVM驗(yàn)證方法學(xué)和System Verilog語(yǔ)言,模塊化實(shí)現(xiàn)了設(shè)計(jì)內(nèi)容及高度的可重用性;設(shè)計(jì)了自動(dòng)化的實(shí)現(xiàn)手段,減少了人為參與過程,提高了驗(yàn)證的可靠性;以反饋方式調(diào)控驗(yàn)證環(huán)境中隨機(jī)測(cè)試激勵(lì)的生成,減少了重復(fù)性驗(yàn)證行為,加速了功能覆蓋率收斂,提高了驗(yàn)證效率。同時(shí),該功能覆蓋率模塊封裝成一個(gè)獨(dú)立功能模塊,易于集成到不同的驗(yàn)證環(huán)境,提升了可移植性。論文最后以SOC芯片上DebugTrace系統(tǒng)中一個(gè)典型模塊的驗(yàn)證過程為例,將功能覆蓋率驅(qū)動(dòng)模塊集成到了該模塊的OVM驗(yàn)證平臺(tái)中并進(jìn)行仿真,通過對(duì)比不同時(shí)刻功能覆蓋率的覆蓋情況得到了功能覆蓋率的收斂曲線。對(duì)比結(jié)果表明采用本文所設(shè)計(jì)的功能覆蓋率驅(qū)動(dòng)模塊使功能覆蓋率的收斂速度提高了50%以上。
[Abstract]:With the rapid development of integrated circuit technology, the scale of chip design is becoming larger and larger, and the function is becoming more and more complex. As a result, the possibility of design defects in the circuit design phase is becoming higher and higher, so the requirement of verification is becoming higher and higher. And now the application field of chip is more and more extensive, and the requirement of design security is also more and more high. The emergence of design loopholes may cause very serious consequences, the adequacy of verification is also particularly important. The market for chip products upgrading requirements are also getting faster and faster. In the front-end design process of large-scale integrated circuit development, verification work has accounted for about 70% of the total workload. How to ensure the adequacy of verification under the premise. Improving the efficiency of verification has become the bottleneck in IC design and development. It is very important to find efficient and feasible verification methods. In this paper, the traditional directional verification methods are compared and analyzed in detail. Based on the randomized incentive verification method with constraints and the coverage driven verification method, this paper aims at the challenges of completeness, reusability, reliability and efficiency faced by the current verification work. Combining the functional coverage driven verification method with the OVM verification methodology. The functional coverage driver component is designed and implemented. The functional coverage driver component designed in this paper realizes the dynamic automatic analysis of the function coverage. According to the analysis results, the sequence generator in the verification platform can generate targeted test incentives, and can be easily integrated into the verification environment of OVM architecture. This module is based on the functional coverage driven verification method. The completeness of verification is realized. Based on OVM verification methodology and System Verilog language, the design content and high reusability are realized by modularization. The realization method of automation is designed to reduce the process of artificial participation and improve the reliability of verification. The generation of random test incentives in the verification environment is regulated by feedback, which reduces the repetitive verification behavior, accelerates the convergence of function coverage, and improves the efficiency of verification. The functional coverage module is encapsulated into a separate functional module, which is easy to integrate into different verification environments. Finally, the verification process of a typical module in DebugTrace system on SOC chip is taken as an example. The function coverage driver module is integrated into the OVM verification platform of the module and simulated. The convergent curve of function coverage is obtained by comparing the coverage of function coverage at different times. The comparison results show that the convergent speed of function coverage is improved by using the function coverage driver module designed in this paper. More than 0%.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN402

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本文編號(hào)：1442117