本文關(guān)鍵詞：固定邊框的多電壓布圖規(guī)劃算法　出處：《電子學(xué)報》2017年08期 　論文類型：期刊論文

  更多相關(guān)文章： 低功耗 多電壓 布圖規(guī)劃 固定邊框

【摘要】：多電壓設(shè)計是應(yīng)對SoC功耗挑戰(zhàn)的一種有效方法,但會帶來線長、面積等的開銷。為減少線長、芯片的空白面積及提高速度,提出了一種改進的固定邊框多電壓布圖方法.對基于NPE(Normalized Polish Expression)表示的布圖解,采用形狀曲線相加算法來計算其最優(yōu)的布圖實現(xiàn),并通過增量計算方法來減少計算NPE及多電壓分配的時間.為使所得布圖解滿足給定的邊框約束,提出了一個考慮固定邊框約束的目標(biāo)函數(shù),并采用刪除后插入(Insertion after Delete,IAD)算子對SA求得布圖解進行后優(yōu)化.實驗結(jié)果表明,和已有方法相比,所提出方法在線長和空白面積率方面有較明顯優(yōu)勢,且所有電路在不同高寬比、不同電壓島數(shù)下均實現(xiàn)了極低的空白面積率(1%).
[Abstract]:Multi-voltage design is an effective method to deal with the power challenge of SoC, but it will bring the cost of line length, area, etc. In order to reduce the line length, the blank area of the chip and improve the speed. In this paper, an improved method of fixed frame multi-voltage layout is proposed. The layout diagram based on NPE(Normalized Polish expression is presented. The shape curve addition algorithm is used to calculate the optimal layout realization, and the incremental calculation method is used to reduce the time of calculating NPE and multi-voltage distribution. In this paper, an objective function considering the constraint of fixed border is proposed, and the insert after Delete is inserted after deletion. The experimental results show that the proposed method has obvious advantages in terms of on-line length and blank area ratio, and all circuits have different aspect ratio of aspect to width. Very low blank area ratio is realized under different voltage islands.
【作者單位】： 寧波大學(xué)科學(xué)技術(shù)學(xué)院;寧波大學(xué)信息科學(xué)與工程學(xué)院;
【基金】：國家自然科學(xué)基金(No.61131001,No.61501268,No.61471211) 浙江省自然科學(xué)基金(No.LY15F030008)
【分類號】：TN47
【正文快照】： 1引言基于多供電電壓(Multiple Supply Voltage,MSV)的設(shè)計方法是降低So C功耗最為有效的方法之一[1~4].它是根據(jù)模塊的性能需求給每個模塊分配合適的供電電壓來實現(xiàn)降低功耗的目的.同時,為降低電源網(wǎng)絡(luò)布線網(wǎng)絡(luò)的復(fù)雜度,在布圖規(guī)劃時需要將相同電壓的模塊匯聚在一起,形成電壓

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