本文關(guān)鍵詞：多通道音頻段正弦信號(hào)發(fā)生技術(shù)的研究　出處：《哈爾濱理工大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 音頻段信號(hào) 多通道 SPWM變換 開關(guān)乘法

【摘要】：在科學(xué)研究和工程實(shí)踐的測(cè)試系統(tǒng)中,往往需要多路信號(hào)作為激勵(lì)源,比如機(jī)械系統(tǒng),水聲探測(cè)系統(tǒng)等。傳統(tǒng)的獲得多通道信號(hào)的方法是使用多個(gè)信號(hào)發(fā)生器/任意波發(fā)生器,使用大量相同的模擬電路和數(shù)字電路的疊加。這種方法的體積大,硬件成本高,功耗大。另一方面,由于每個(gè)信號(hào)源都使用獨(dú)立的時(shí)鐘晶振,即使時(shí)鐘晶振的絕對(duì)誤差和溫漂系數(shù)極小,由于時(shí)間的累積,各通道輸出的激勵(lì)經(jīng)過長(zhǎng)時(shí)間的工作之后,通道間的信號(hào)不匹配,程度加大。因此,多路激勵(lì)系統(tǒng)需要解決兩大關(guān)鍵技術(shù),一是電路的小尺寸和低功耗,二是通道信號(hào)間的同步問題。現(xiàn)在數(shù)字技術(shù)發(fā)展迅猛,特別是大容量、高速度的CPLD/FPGA的廣泛使用。本文充分利用CPLD/FPGA的數(shù)字資源,對(duì)多通道的音頻段正弦信號(hào)的發(fā)生方法進(jìn)行研究,并對(duì)電路進(jìn)行設(shè)計(jì)和仿真。首先研究了有存儲(chǔ)資源的基于FPGA的多通道音頻段正弦信號(hào)發(fā)生方法,FPGA內(nèi)嵌RAM資源,可以將正弦波形表固化在FPGA中,利用SPWM波形變換原理,研究擴(kuò)展通道的數(shù)量與FPGA資源的關(guān)系,并進(jìn)行模擬電路設(shè)計(jì)。對(duì)8通道的SPWM邏輯信號(hào)進(jìn)行仿真設(shè)計(jì),并以三通道為例在音頻的范圍內(nèi)實(shí)現(xiàn)正弦信號(hào)的發(fā)生。SPWM邏輯信號(hào)的仿真設(shè)計(jì)以及正弦信號(hào)的發(fā)生表明,該方法可以在音頻范圍內(nèi)實(shí)現(xiàn)其多通道的信號(hào)發(fā)生,其頻率可達(dá)到10kHz。線路簡(jiǎn)單,只需要一根信號(hào)輸入線即可,充分利用了數(shù)字資源,占用FPGA內(nèi)部的RAM資源,并且其通道數(shù)取決去FPGA內(nèi)的RAM資源。此外,各個(gè)通道間的信號(hào)還可以實(shí)現(xiàn)隔離。接著研究了無存儲(chǔ)資源的多通道音頻段正弦信號(hào)的發(fā)生方法,利用開關(guān)乘法正弦發(fā)生原理來實(shí)現(xiàn),分別基于CPLD對(duì)8通道和基于FPGA對(duì)56通道的控制電路進(jìn)行仿真設(shè)計(jì),然后,同樣以三通道為例,在音頻的范圍內(nèi),對(duì)開關(guān)乘法正弦變換電路進(jìn)行設(shè)計(jì)。該方法不在需要占用RAM資源,從而易于更好的擴(kuò)展通道的個(gè)數(shù),其線路數(shù)為2N+1,其中N為通道數(shù)。
[Abstract]:In the test system of scientific research and engineering practice, often require multiple signals as the excitation source, such as mechanical system, underwater acoustic detection system. The traditional method to obtain multi-channel signal is to use multiple signal generator / arbitrary wave generator, used together with large numbers of identical analog circuits and digital circuits. This method of large volume hardware, high cost, high power consumption. On the other hand, because each source is independent of the clock, the clock even if the absolute error and the temperature drift coefficient is extremely small, due to the accumulation of time, the output of each channel excitation after long time working, the signal channel does not match the degree of increase. Therefore, multiple incentive system needs to solve two key technologies, is a small size and low power consumption circuit, two channel signal synchronization between. Now the rapid development of digital technology, especially large capacity, high The widespread use of the speed of CPLD/FPGA. This paper makes full use of digital resources of CPLD/FPGA, research method of multi channel audio Duan Zhengxian signal, and the design and Simulation of the circuit. Firstly, storage resources for the FPGA multi channel audio frequency sinusoidal signal generating method based on FPGA, embedded RAM resources can be sine wave shape curing in FPGA, using SPWM waveform transform principle, the relationship between resource quantity and FPGA study on the expansion of channels, and analog circuit design. The simulation design of SPWM logic signals of 8 channels, and three channels to realize in the audio range of sinusoidal signal.SPWM signal simulation and logic design sine wave signal generating signals show that this method can realize the multi channel in the audio range, the frequency can reach 10kHz. simple circuit, only one signal input line To make full use of the digital resources, occupy the FPGA RAM internal resources, and the number of channels depends on to FPGA within the RAM resources. In addition, each channel between the signal can also achieve isolation. Then study the method without storage resources of multi channel audio frequency sinusoidal signal, using the switching principle to realize sine multiplication based on the CPLD of 8 channels respectively, and the control circuit of the 56 channel FPGA based on simulation design, then, the same three channel as an example, in the audio range, the design of the switching circuit multiplication sine transform. This method does not occupy RAM resources in need, the number of which is easy to extend channel better, the the line number is 2N+1, where N is the number of channels.

【學(xué)位授予單位】：哈爾濱理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN702

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