本文關(guān)鍵詞：8位20KSPS 0.4V超低功耗SAR ADC的研究　出處：《西安電子科技大學(xué)》2015年碩士論文　論文類(lèi)型：學(xué)位論文

  更多相關(guān)文章： 逐次逼近型ADC 低功耗 開(kāi)關(guān)時(shí)序 泄漏功耗

【摘要】：逐次逼近型模數(shù)轉(zhuǎn)換器(SAR ADC)是一種具有中等采樣速度和中等轉(zhuǎn)換精度的ADC,它具有結(jié)構(gòu)簡(jiǎn)單,面積小,成本低廉,能耗低等優(yōu)點(diǎn),廣泛運(yùn)用于無(wú)線(xiàn)傳感網(wǎng)絡(luò),便攜式設(shè)備,醫(yī)療電子,精密儀器儀表等等場(chǎng)合。隨著工藝技術(shù)的進(jìn)步,工藝尺寸進(jìn)一步縮小,給數(shù)字電路設(shè)計(jì)帶來(lái)了飛速的發(fā)展,對(duì)于模數(shù)轉(zhuǎn)換器,特別是SAR ADC,由于SAR ADC中,模擬電路模塊比較少,所以更為適應(yīng)工藝的進(jìn)步,工藝的進(jìn)步給SAR ADC帶了飛躍發(fā)展。近年來(lái),SAR ADC憑借著其獨(dú)特的性能優(yōu)勢(shì),越來(lái)越受到國(guó)內(nèi)外廣泛的科研團(tuán)體的青睞,高速高精度低功耗SAR ADC的設(shè)計(jì)取得了顯著成果,涌現(xiàn)出一系列性能優(yōu)異的芯片設(shè)計(jì)。本文設(shè)計(jì)了一款8位20KSPS 0.4V超低功耗SAR ADC。通過(guò)對(duì)已有的各種關(guān)于電荷再分配結(jié)構(gòu)時(shí)序的研究,提出了一種新型節(jié)能的電容開(kāi)關(guān)時(shí)序,該結(jié)構(gòu)巧妙的運(yùn)用了整體切換的方式,極大的降低了時(shí)序切換過(guò)程中的轉(zhuǎn)換能量。通過(guò)對(duì)幾種不同時(shí)序開(kāi)關(guān)的MATLAB建模仿真分析,與傳統(tǒng)的開(kāi)關(guān)時(shí)序?qū)Ρ?新型開(kāi)關(guān)時(shí)序可以將電容的功耗和面積分別節(jié)省99.9%和75%。由于電容轉(zhuǎn)換網(wǎng)絡(luò)所消耗的能耗占整個(gè)系統(tǒng)的比重最大,因此,采用新型開(kāi)關(guān)時(shí)序,能夠非常有效的降低整個(gè)系統(tǒng)的能耗。由于系統(tǒng)電源電壓比較低,采用一級(jí)柵壓自舉電路無(wú)法使得MOS管完全導(dǎo)通,給系統(tǒng)引入了極大的非線(xiàn)性,因此,本文采用了二級(jí)柵壓自舉結(jié)構(gòu)。低壓低速情況下,電荷泄漏情況比較嚴(yán)重,為了減小電荷泄漏所帶來(lái)的誤差,在ADC系統(tǒng)的邏輯結(jié)構(gòu)中使用了可再生鎖存的方式。在版圖設(shè)計(jì)中,將模擬電路和數(shù)字電路之間設(shè)計(jì)一定的物理隔離,并且添加保護(hù)環(huán),提高了系統(tǒng)的抗干擾能力。部分MOS管采用了雙阱工藝,抑制閂鎖效應(yīng)。對(duì)電路各個(gè)模塊版圖采用了對(duì)稱(chēng)共質(zhì)心布局,并且電容陣列周?chē)尤肱阋r電容,以提高整個(gè)電容陣列的匹配性。在比較器兩個(gè)輸入對(duì)管周?chē)尤雂ummy管,以減小失配的影響。本文設(shè)計(jì)基于SMIC0.18μm CMOS工藝,完成版圖設(shè)計(jì)后,整體芯片面積為1070×1240?m2。在0.4V電源電壓下,20KSPS采樣率下,本論文所設(shè)計(jì)的超低功耗SAR ADC的ENOB為7.98bit,SNDR為49.799dB,SFDR為73.83dB,THD為69.55dB,功耗為19.76nW,功耗的優(yōu)值FOM為3.86fJ/conversion-step。
[Abstract]:Successive approximation analog-to-digital converter (ADCA / D) is a kind of ADCs with moderate sampling speed and medium conversion accuracy. It has the advantages of simple structure, small area, low cost and low energy consumption. It is widely used in wireless sensor networks, portable devices, medical electronics, precision instruments and other occasions. With the progress of technology, the process size is further reduced, which brings rapid development to the design of digital circuits. For analog-to-digital converters, especially SAR ADC, because of the small number of analog circuit modules in SAR ADC, it is more suitable for the progress of technology. The progress of technology has brought a great development to SAR ADC. In recent years, SAR ADC has been more and more popular with a wide range of scientific research organizations at home and abroad because of its unique performance advantages. The design of high speed, high precision and low power SAR ADC has achieved remarkable results. A series of excellent chip designs have emerged. An 8-bit 20KSPS 0.4V ultra-low power SAR is designed in this paper. ADC. through the existing research on the time series of charge redistribution structure. In this paper, a new type of energy saving capacitor switch timing is proposed, which makes use of the whole switching mode skillfully. It greatly reduces the switching energy in the process of timing switching. Through modeling and simulation analysis of several different timing switches, compared with the traditional switch timing. The new switching sequence can save the power consumption and area of the capacitor by 99.9% and 75, respectively. Because the energy consumption of the capacitive switching network is the largest in the whole system, the new switch timing is adopted. It can reduce the energy consumption of the whole system very effectively. Because the power supply voltage of the system is relatively low, the MOS transistor can not be completely switched on by using the first stage gate voltage bootstrap circuit, which brings a great deal of nonlinearity to the system. In this paper, the two-stage gate voltage bootstrap structure is used. At low voltage and low speed, the charge leakage is serious, in order to reduce the error caused by charge leakage. In the logical structure of ADC system, the method of renewable latch is used. In the layout design, the physical isolation between analog circuit and digital circuit is designed, and the protection ring is added. The anti-interference ability of the system is improved. Some MOS transistors adopt double well technology to suppress latch effect. The layout of each module adopts symmetrical co-centroid layout and the capacitor array is surrounded by a foil capacitor. In order to improve the matching performance of the whole capacitor array, the dummy tube is added around the comparator's two inputs to reduce the mismatch. The design of this paper is based on the SMIC0.18 渭 m CMOS process. After layout design, the overall chip area is 1070 脳 1240? At the sampling rate of 20KSPS at 0.4V power supply, the ENOB of the ultra-low power SAR ADC designed in this paper is 7.98bit. The SNDR was 49.799dBU SFDR (73.83dBN) and the power consumption was 19.76nW. The FOM of power consumption is 3.86fJ / conversion-step.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN792

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