發(fā)布時(shí)間：2018-01-12 16:43

  本文關(guān)鍵詞：網(wǎng)絡(luò)芯片物理編碼子層關(guān)鍵電路的設(shè)計(jì)及驗(yàn)證　出處：《西安電子科技大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 網(wǎng)絡(luò)芯片 光纖通道 交換機(jī)芯片 物理編碼子層 SoC

【摘要】：隨著互聯(lián)網(wǎng)技術(shù)的快速發(fā)展,人類的生活越來越離不開網(wǎng)絡(luò)。在生活服務(wù)等相關(guān)領(lǐng)域,無時(shí)無刻都要進(jìn)行信息之間的傳輸。而網(wǎng)絡(luò)芯片,在其中一直扮演著重要的角色。目前,對(duì)網(wǎng)絡(luò)芯片的研究中,由于編碼校驗(yàn)是數(shù)據(jù)進(jìn)行可靠通信的保障,編碼校驗(yàn)的效率也是決定芯片面積的重要因素,因此,對(duì)于網(wǎng)絡(luò)芯片中物理編碼子層的研究越來越重要。因而,本課題基于對(duì)一種網(wǎng)絡(luò)芯片——光纖通道交換機(jī)芯片物理編碼子層的研究,基于光纖通道技術(shù)的優(yōu)勢,并且采用SoC設(shè)計(jì)流程,完成了物理編碼子層關(guān)鍵電路的設(shè)計(jì)驗(yàn)證工作,并且實(shí)現(xiàn)了可復(fù)用IP的設(shè)計(jì)。本文主要完成的工作包括:1.在設(shè)計(jì)初期,深入研究了相關(guān)基礎(chǔ)理論,包括物理層結(jié)構(gòu)和光纖通道技術(shù)。在深入理解光纖通道協(xié)議和物理編碼子層功能的基礎(chǔ)上,對(duì)該芯片物理編碼子層的編碼和校驗(yàn)算法進(jìn)行了研究。綜合各方面因素,探究適合光纖通道交換機(jī)芯片的編碼技術(shù)和校驗(yàn)算法。2.基于光纖通道協(xié)議,采用當(dāng)前SoC設(shè)計(jì)技術(shù),分析了光纖通道交換機(jī)芯片的體系架構(gòu),提出了適合片上系統(tǒng)設(shè)計(jì)的光纖通道交換機(jī)芯片PCS關(guān)鍵電路具體功能特性要求。根據(jù)PCS模塊的具體功能,提出了PCS關(guān)鍵電路的設(shè)計(jì)方案,分別從發(fā)送和接收兩部分詳細(xì)介紹了各個(gè)子模塊的設(shè)計(jì)。發(fā)送部分的設(shè)計(jì)中,實(shí)現(xiàn)了8B/10B的編碼、發(fā)送緩沖區(qū)以及偽隨機(jī)碼產(chǎn)生器的設(shè)計(jì);接收部分的設(shè)計(jì)中,實(shí)現(xiàn)了8B/10B的解碼、接收彈性緩沖區(qū)、Comma的檢測和校準(zhǔn)以及CRC校驗(yàn)等子模塊的設(shè)計(jì),最終實(shí)現(xiàn)了PCS模塊的設(shè)計(jì)。并且基于光纖通道交換機(jī)芯片的研究,本文提出了一種可復(fù)用的PCS關(guān)鍵電路的設(shè)計(jì)技術(shù)。3.在模塊設(shè)計(jì)實(shí)現(xiàn)后,進(jìn)行了PCS關(guān)鍵電路的模塊級(jí)功能仿真、系統(tǒng)級(jí)虛擬平臺(tái)仿真驗(yàn)證以及FPGA的實(shí)現(xiàn)。模塊級(jí)仿真中,首先,根據(jù)需求規(guī)范、功能規(guī)范等編寫驗(yàn)證規(guī)范,編寫測試項(xiàng);然后根據(jù)策劃的驗(yàn)證項(xiàng),編寫測試用例,對(duì)模塊進(jìn)行了驗(yàn)證。系統(tǒng)級(jí)虛擬平臺(tái)驗(yàn)證中,通過添加不同的總線功能模型,構(gòu)成交換機(jī)芯片工作所需的最小虛擬系統(tǒng);然后在交換機(jī)芯片其他外設(shè)接口上,通過編寫相應(yīng)的測試模型,模擬該外設(shè)的輸入和輸出操作,在虛擬的驗(yàn)證環(huán)境中完成仿真驗(yàn)證。FPGA實(shí)現(xiàn)中,主要是通過綜合優(yōu)化,對(duì)其資源和功耗進(jìn)行了分析。最終實(shí)現(xiàn)了PCS關(guān)鍵電路的仿真和驗(yàn)證。
[Abstract]:With the rapid development of Internet technology, the human life is more and more cannot do without the network. The service life and other related fields, to transmit information between every hour and moment. And the network chip, has played an important role in them. At present, the research of network chip, because the encoding check is data for reliable communication security check encoding efficiency is an important factor determining the chip area, therefore, is very important for studying the physical network layer encoding chip more and more. Therefore, the research on a network switch chip -- physical encoding chip sub layer based on fiber channel technology based on the advantages of using SoC and design complete the design process, verification of the key circuit physical layer encoding, and realizes the design of reusable IP. The main work includes: 1. in the design stage, Deep research on the related basic theory, including the physical layer structure and fiber channel technology. Based on deep understanding of the fibre channel protocol and physical layer encoding function, encoding and calibration algorithm of the physical layer encoding chip was studied. Various factors, to explore suitable for fiber channel switch chip encoding and calibration technology.2. algorithm based on fibre channel protocol, using the SoC design technology, analyzes the architecture of fiber channel switch chip, proposed requirements for specific functional characteristics of key circuit fiber channel switch chip PCS system on chip design. According to the specific function of the PCS module, put forward a design scheme of PCS key circuit, respectively, from the sending and receiving the two part introduces the design of each sub module. The design of the transmit part, implementation of the 8B/10B encoding, sending buffer and pseudo random code Generator design; design of the receiving part, realize 8B/10B decoding, receiving elastic buffer, Comma testing and calibration and CRC check module design, finally realizes the design of PCS module. And based on fibre channel switch chip, this paper presents a reusable PCS key circuit the design of.3. technology in the design and Realization of the module, the module function simulation PCS key circuit, system level simulation of virtual platform and the implementation of FPGA. The module level simulation, firstly, according to the requirements of specifications, functional specifications written verification specification, write test items; then according to the validation plan, write test case the module was tested, the system level virtual platform, by adding different bus function model, a minimum system for the virtual switch chip work; then in the switch chip Other peripheral interface, through the preparation of the corresponding test model, analog input and output operation of the peripherals, in a virtual environment to verify the complete simulation.FPGA implementation, mainly through the comprehensive optimization of its resources and power consumption are analyzed. Finally the simulation and verification of PCS key circuit.

【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN402;TN929.11

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本文編號(hào)：1415118