本文關鍵詞：基于單速率濾波器組技術的高效數(shù)字信道化接收算法研究及FPGA實現(xiàn)　出處：《東南大學》2015年碩士論文　論文類型：學位論文

  更多相關文章： 數(shù)字信道化 快速濾波器組 FPGA 性能測試

【摘要】：數(shù)字信道化接收機具有瞬時帶寬大、動態(tài)范圍大、頻率選擇性能好等諸多優(yōu)點,在現(xiàn)代電子戰(zhàn)中具有重要作用。針對以多相濾波器組為核心的數(shù)字信道化技術復雜度高、相鄰通道的可拼接性較差等問題,本文研究基于單速率濾波器組技術的數(shù)字信道化算法及FPGA實現(xiàn)。論文的主要工作包括：研究了用于實現(xiàn)數(shù)字信道化結構的單速率濾波器組算法及其相關算法,基于PXIe模塊化虛擬儀器,在Labview FPGA平臺上實現(xiàn)了數(shù)字信道化接收機核心模塊及其外圍功能模塊,并完成了人機交互界面設計及性能測試。首先,介紹了數(shù)字信道化技術研究的背景及意義,并通過分析國內外研究現(xiàn)狀,認識到國內對數(shù)字信道化技術的研究還很不足,由此得出研究數(shù)字信道化技術的算法及實現(xiàn)是十分有必要的。然后,介紹了數(shù)字信道化接收機的整體架構,分析了比較常用的信道化結構即基于FFT的信道化結構的原理和缺陷,以及可以彌補FFT濾波性能欠缺的可能途徑。其一,基于多相濾波器組的信道化方法可以克服FFT濾波器階數(shù)與點數(shù)之間固定關系的限制,但是需要較多的乘法器資源。其二,基于快速濾波器組(FFB)的信道化方法,不但能彌補FFT原型子濾波器濾波性能不佳的缺陷,設計高性能的濾波器組參數(shù)；而且基于頻罩法設計子濾波器系數(shù),與FFT比較復雜度基本相當。本節(jié)首先研究了FFB算法的推導、基于頻罩法的子濾波器系數(shù)的設計和基于節(jié)點調制的FFB改進算法。其次比較了FFT,多相濾波器組和FFB在濾波性能、乘法器消耗量和應用場景等方面的性能。最后進一步研究了諸如子信道抽取算法和子信道有效數(shù)據(jù)檢測算法的信道化后續(xù)處理算法。接著,本節(jié)在PXIe模塊化儀器上基于Labview FPGA平臺設計并實現(xiàn)了50MHz分析帶寬、64通道數(shù)字信道化接收機。首先闡述了系統(tǒng)各個模塊的設計思想,然后詳細描述了各個模塊的實現(xiàn)過程。系統(tǒng)模塊包括數(shù)字信道化核心模塊、數(shù)字信道化后續(xù)處理模塊、高速數(shù)據(jù)傳輸模塊、射頻信號流盤模塊和射頻信號回放模塊。數(shù)字信道化核心模塊是整個系統(tǒng)的核心,實現(xiàn)源采樣信號的信道化濾波：數(shù)字信道化后續(xù)處理模塊包括子信道的下采樣模塊和信道檢測模塊,實現(xiàn)子信道的有效數(shù)據(jù)檢測和降速處理；高速數(shù)據(jù)傳輸模塊實現(xiàn)FPGA與主控器之間的高速信息交互與可靠實時傳輸；射頻信號流盤模塊和射頻信號回放模塊用來進行源采樣數(shù)據(jù)的錄制和多次回放分析。最后,介紹了整個系統(tǒng)的硬件儀器的搭建包括矢量信號分析儀的搭建和矢量信號發(fā)生器的搭建,并在Labview FPGA平臺上對整個數(shù)字信道化接收機系統(tǒng)進行了性能測試,將測試結果與理論結果進行分析對比,驗證了系統(tǒng)的正確性。
[Abstract]:Digital channelized receiver has many advantages, such as large instantaneous bandwidth, large dynamic range and good frequency selection performance. It plays an important role in modern electronic warfare. The digital channelization technology with polyphase filter banks as the core has high complexity and poor splicing ability of adjacent channels. In this paper, the digital channelization algorithm based on single-rate filter banks and its FPGA implementation are studied. The main work of this thesis is as follows:. A single rate filter bank algorithm and its related algorithms for digital channelization are studied. Based on PXIe modular virtual instrument, the core module of digital channelized receiver and its peripheral function module are realized on Labview FPGA platform. The human-computer interface design and performance test are completed. Firstly, the background and significance of digital channelization research are introduced, and the current research situation at home and abroad is analyzed. It is very necessary to study the algorithm and implementation of digital channelization technology. Then, the whole architecture of digital channelization receiver is introduced. This paper analyzes the principle and defects of the channelized structure based on FFT, and the possible ways to make up for the lack of FFT filtering performance. The channelization method based on polyphase filter banks can overcome the limitation of the fixed relationship between the order and the number of FFT filters, but it needs more multiplier resources. The channelization method based on fast filter banks can not only make up for the poor filtering performance of FFT prototype sub-filters, but also design high performance filter bank parameters. Moreover, the design of subfilter coefficients based on the frequency mask method is similar to that of FFT. In this section, the derivation of FFB algorithm is first studied. The design of subfilter coefficients based on frequency mask method and the improved FFB algorithm based on node modulation. Secondly, the filtering performance of FFT, polyphase filter banks and FFB are compared. The performance of multiplier consumption and application scenarios. Finally, the channelized follow-up processing algorithms such as subchannel extraction algorithm and subchannel effective data detection algorithm are further studied. In this section, 50MHz analysis bandwidth is designed and implemented on PXIe modular instrument based on Labview FPGA platform. Firstly, the design idea of each module of the system is introduced, and then the realization process of each module is described in detail. The system module includes the core module of digital channelization. Digital channelization follow-up processing module, high-speed data transmission module, radio frequency signal streaming disk module and radio frequency signal playback module. Digital channelization core module is the core of the whole system. To realize channelization filtering of source sampling signal: digital channelization follow-up processing module includes subchannel downsampling module and channel detection module to realize effective data detection and speed reduction of subchannel; The high-speed data transmission module realizes the high-speed information exchange and reliable real-time transmission between the FPGA and the main controller. The radio frequency signal stream disc module and the radio frequency signal playback module are used to record the source sampling data and analyze the multiple playback data. Finally. The hardware structure of the whole system includes the construction of the vector signal analyzer and the construction of the vector signal generator. The performance of the whole digital channelized receiver system is tested on the Labview FPGA platform. The correctness of the system is verified by comparing the test results with the theoretical results.
【學位授予單位】：東南大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN713;TN971;TN851

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本文編號：1406922