本文關(guān)鍵詞：基于180nm CMOS工藝的SAR ADC優(yōu)化設(shè)計研究　出處：《中國科學技術(shù)大學》2017年碩士論文　論文類型：學位論文

  更多相關(guān)文章： 電荷測量 LHAASO WCDA SAR ADC 電容失配

【摘要】：在粒子物理實驗中,探測器首先將粒子攜帶的物理信息轉(zhuǎn)化為電信號,再由讀出電子學系統(tǒng)處理,測量信號的時間、電荷等信息。其中電荷測量占有重要地位,其測量結(jié)果對應粒子與探測器相互作用過程中的能量損失,因而對測量能譜、識別成分等有重要作用。成形放大結(jié)合數(shù)字尋峰方法是電荷測量中的一種常用技術(shù),可以實現(xiàn)高測量精度和線性,因此得到廣泛的研究和使用。此方案中輸入信號經(jīng)放大、成形后通過模擬-數(shù)字變換器(Analog-to-Digital Converter,ADC)進行數(shù)字化,再配合數(shù)字尋峰邏輯實現(xiàn)電荷測量。ADC電路是其中的核心組成部分,其性能指標直接影響整個系統(tǒng)的測量精度。在大型物理試驗中,其海量的通道數(shù)對電子學設(shè)計提出了高集成度、低功耗的要求,因此基于專用集成電路(Application Specific Integrated Circuit,ASIC)技術(shù)進行電路集成有重要意義。因為逐次逼進型ADC(Successive Approximation Register ADC,SAR ADC)有低功耗的優(yōu)點,且可以經(jīng)過優(yōu)化設(shè)計滿足采樣率和分辨率的需求,所以成為了物理實驗讀出電子學研究的一個熱點。本論文研究工作集中在SARADC的優(yōu)化設(shè)計上,實際結(jié)合國家重大基礎(chǔ)設(shè)施中關(guān)鍵探測器讀出需求,進行了 ASIC的設(shè)計和測試。其應用背景為大型高海拔空氣簇射觀測站(Large High Altitude Air Shower Observatory,LHAASO)中的水切侖科夫輻射探測器陣列(Water Cherenkov Detector Array,WCDA),在總面積約8萬平方米的范圍內(nèi),電子學系統(tǒng)需要對3120個光電倍增管(Photo-Multiplier Tube,PMT)進行大動態(tài)范圍(1~4000光電子)高精度時間和電荷測量。針對此應用需求,本論文工作中基于180 nm CMOS工藝研究了ADC ASIC的優(yōu)化設(shè)計方法,著重于其性能的優(yōu)化與提升。文章組織結(jié)構(gòu)如下:第一章先介紹了電荷測量方法,然后介紹了 LHAASO WCDA的研究背景及其電子學整體設(shè)計、指標要求,最后明確了此應用對于ADC ASIC的性能要求。第二章介紹了 ADC基本概念、一些有代表性的ADC結(jié)構(gòu)的工作過程和性能特點以及性能指標,并且調(diào)研了粒子物理實驗中使用的ADC ASIC。這為本論文的優(yōu)化設(shè)計工作提供了參考。第三章介紹了 SAR ADC優(yōu)化設(shè)計方案。首先根據(jù)設(shè)計指標分析了 SAR ADC性能提升的瓶頸,闡述了影響ADC性能的最主要因素即ASIC中電容型數(shù)模轉(zhuǎn)換器(Digital-to-Analog Converter,DAC)的非線性,來源于電容失配。然后對電容失配問題進行了調(diào)研分析,并提出了優(yōu)化設(shè)計方案。第四章介紹了驗證ASIC電路設(shè)計。詳細陳述了 SAR ADC的關(guān)鍵電路模塊以及多方案下多通道電路的設(shè)計方案。第五章介紹了驗證ASIC的系統(tǒng)測試結(jié)果�；贗EEE的ADC測試標準建立了測試系統(tǒng)并進行了一系列測試。結(jié)果表明,通過電路的優(yōu)化設(shè)計,在基帶上限輸入信號頻率下信號噪聲失真比(Signal to Noise and Distortion Ratio,SINAD)指標提升了約4 dB;采樣率31.25 Msps工作條件下,輸入信號頻率在整個基帶范圍內(nèi)時,有效位都好于9 bits。最后一章中總結(jié)了論文工作,并展望了下一步工作規(guī)劃。
[Abstract]:In particle physics experiment, the detector first physical particles carrying information into electrical signals by the readout electronics system, measurement time, charge and other information. The charge measurement occupies an important position, the energy loss of the measurement results of the interaction process and corresponding particle detector, so the measurement of energy spectrum recognition composition is important. The peak search method based on digital shaping amplifier is a commonly used technique in the charge measurement, can achieve high measurement accuracy and linearity, so has been widely studied and used. In the scheme, the input signal is amplified, formed by an analog to digital converter (Analog-to-Digital Converter, ADC) were digitized with digital peak charge measurement of.ADC logic circuit is one of the core components, its performance directly affects the precision of the whole system in the large. The physical test, the number of channels for its massive electronics design was proposed for high integration, low power requirements, therefore based on ASIC (Application Specific Integrated Circuit, ASIC) has important significance for the integrate circuit technology. Because successive type ADC (Successive Approximation Register on ADC, SAR ADC) has the advantages of low power consumption. And can be optimized to meet the sampling rate and resolution of the demand, so become a hot research read physical experiment. This thesis focused on the optimization design of SARADC, combined with the actual reading demand in key national key infrastructure in the detector, the design and test of ASIC. The application background of large scale high an air shower Observatory (Large High Altitude Air Shower Observatory, LHAASO) in the water Cerenkov radiation detector array (Water Cherenk Ov Detector Array, WCDA), in the range of the total area of about 80 thousand square meters, the electronics system for 3120 photomultiplier tubes (Photo-Multiplier, Tube, PMT) of high dynamic range (1~4000 photoelectron) high precision time and charge measurement. According to the application demand, optimization design method of 180 nm CMOS process is studied based on ADC the work of the ASIC theory, focus on optimizing and improving its performance. The following article structure: the first chapter introduces the charge measurement method, and then introduces the research background of LHAASO WCDA and its electronics overall design requirements, and finally clear this application on the performance of ADC ASIC. The second chapter introduces the ADC the basic concept, some ADC structure representative of the work process and the performance characteristics and performance index, and research the use of particle physics experiments in the ADC ASIC. for the optimization design of Engineering For reference. The third chapter introduces the SAR ADC optimization. Firstly, the bottleneck of SAR ADC performance analysis according to the design index, expounds the main factors affecting the performance of ADC is capacitive ASIC DAC (Digital-to-Analog Converter, DAC) derived from the nonlinear capacitor mismatch. Then the research analysis of capacitor mismatch problems, and puts forward the optimized design scheme. The fourth chapter introduces the verification of ASIC circuit design. A detailed statement of the design of multi-channel circuit key circuit module of SAR ADC and multi scheme. The fifth chapter introduces the system test results verify ASIC. ADC test based on the standard IEEE testing system has been established. And conducted a series of tests. The results showed that by optimizing the circuit design, the upper limit frequency of the input signal in the baseband signal to noise and distortion ratio (Signal to Noise and Distortion Ratio, S INAD) the index has increased by about 4 dB, and the sampling rate is 31.25 Msps. When the input signal frequency is in the whole baseband range, the effective bits are all better than 9 bits.. The last chapter summarizes the work of the paper, and looks forward to the next step work plan.

【學位授予單位】：中國科學技術(shù)大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN792

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本文編號：1385938