本文關(guān)鍵詞：面向三維高密度集成系統(tǒng)的多物理場耦合算法的研究與開發(fā)　出處：《東南大學(xué)》2016年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 三維熱阻網(wǎng)絡(luò)模型 溫度分布 單層芯片結(jié)構(gòu) 多層芯片堆疊結(jié)構(gòu)

【摘要】：隨著社會(huì)的發(fā)展,汽車電子、航天工業(yè)、通訊、計(jì)算機(jī)等現(xiàn)代行業(yè)對功能更強(qiáng)、尺寸更小、集成度更高的便攜式電子產(chǎn)品的要求愈加強(qiáng)烈。單層芯片結(jié)構(gòu),從DIP(雙列直插式)到MCM(多芯片),面積的利用率越來越高,適用頻率、可靠性也越來越高,更加方便耐用,但仍停留在二維平面結(jié)構(gòu)上,無法滿足現(xiàn)代行業(yè)的需求,因此更高密度的多層堆疊結(jié)構(gòu)被提出。由于溫度對芯片的影響,在單層芯片的二維結(jié)構(gòu)上,隨著功率密度的增大而增大,因此熱管理也變的更加重要。而堆疊結(jié)構(gòu)的復(fù)雜度和功率密度更高,溫度對結(jié)構(gòu)的影響也更大。因此,無論單芯片結(jié)構(gòu)還是多芯片結(jié)構(gòu),對熱管理都非常必要,需要建立準(zhǔn)確、高效的三維傳熱模型。本文主要工作有：(1)以傅里葉熱傳導(dǎo)理論和熱對流理論為基礎(chǔ),建立熱阻模型。通過將芯片結(jié)構(gòu)合理劃分為多個(gè)區(qū)域,計(jì)算各個(gè)區(qū)域熱阻,得到x、y和z的熱阻總和,進(jìn)而得到熱源區(qū)域最高溫度點(diǎn)的溫度值和邊界平均溫度。由于三維溫度的擴(kuò)算,類似于球壁導(dǎo)熱,故對于節(jié)點(diǎn)之間的溫度分布,采用球壁導(dǎo)熱的原理進(jìn)行計(jì)算。最終建立了三維傳熱熱阻網(wǎng)絡(luò)模型的基礎(chǔ)理論模型,包括：熱源中心溫度模型、溫度分布模型和迭代計(jì)算法�；谌S傳熱熱阻網(wǎng)絡(luò)模型的基礎(chǔ)理論模型,得到單層芯片結(jié)構(gòu)熱阻網(wǎng)絡(luò)模型和多層芯片堆疊結(jié)構(gòu)熱阻網(wǎng)絡(luò)模型,并分別作出相應(yīng)的熱阻分析圖。對于對流熱阻的分析,創(chuàng)新性的采用迭代計(jì)算的方法,來計(jì)算對流熱阻對應(yīng)的對流系數(shù)。(2)用ANSYS仿真驗(yàn)證三維傳熱熱阻網(wǎng)絡(luò)模型的正確性,以三維傳熱熱阻網(wǎng)絡(luò)模型理論計(jì)算的參數(shù)作為ANSYS建模的參數(shù),將三維傳熱熱阻網(wǎng)絡(luò)模型理論計(jì)算中使用的功率和迭代得到的對流系數(shù)作為ANSYS計(jì)算模型的負(fù)載,并對二者的數(shù)據(jù)進(jìn)行對比驗(yàn)證。結(jié)果顯示在不同的生熱率和熱源尺寸下,熱源中心最高溫度點(diǎn)的溫度值與Ansys仿真結(jié)果誤差在10%以內(nèi),顯示了三維傳熱熱阻網(wǎng)絡(luò)模型的準(zhǔn)確性。(3)通過對專用熱阻測試芯片進(jìn)行實(shí)驗(yàn)測試,并將實(shí)驗(yàn)測試結(jié)果與單層芯片結(jié)構(gòu)的三維傳熱熱阻網(wǎng)絡(luò)模型理論計(jì)算結(jié)果以及ANSYS仿真結(jié)果進(jìn)行對比,得到三維傳熱熱阻網(wǎng)絡(luò)模型與實(shí)驗(yàn)測試的誤差和ANSYS仿真與實(shí)驗(yàn)測試的誤差都在10%以內(nèi),從實(shí)驗(yàn)的角度驗(yàn)證了三維傳熱熱阻網(wǎng)絡(luò)模型的準(zhǔn)確性。(4)為了提高工作效率,將計(jì)算機(jī)輔助分析應(yīng)用于堆疊結(jié)構(gòu)的熱阻網(wǎng)絡(luò)模型建模與仿真,開發(fā)了基于Windows平臺(tái)的熱分析軟件。該軟件以VC++為主要開發(fā)工具,具有界面友好、操作簡單、可移植性好,分析精度較高,對多層芯片堆疊結(jié)構(gòu)的熱設(shè)計(jì)有一定的輔助作用。本文建立的三維傳熱熱阻網(wǎng)絡(luò)模型,可適用于單層和多層芯片結(jié)構(gòu),能夠快速、有效的獲得相應(yīng)的三維溫度分布。通過ANSYS仿真軟件和專用熱阻測試芯片的實(shí)驗(yàn)測試對三維傳熱熱阻網(wǎng)絡(luò)模型進(jìn)行了驗(yàn)證,證明了該熱阻網(wǎng)絡(luò)模型的正確性和有效性。在單層和多層堆疊芯片結(jié)構(gòu)的設(shè)計(jì)中,該三維傳熱熱阻網(wǎng)絡(luò)模型對熱設(shè)計(jì)有一定的參考價(jià)值。
[Abstract]:With the development of society, automotive electronics, aerospace industry, communications, computers and other modern industries are more demanding for portable electronic products with stronger functions, smaller size and higher integration. Single chip structure, from DIP (dual-in-line) to MCM (multi chip), area utilization rate is higher and higher, frequency of application, the reliability is also more and more high, more convenient and durable, but still remain in the two-dimensional plane, unable to meet the modern industry demand, so the high density multilayer stack structure is put forward. Due to the influence of temperature on the chip, the two dimensional structure of single-layer chip increases with the increase of the power density, so the heat management becomes more important. The complexity and power density of the stacked structure are higher, and the temperature has more influence on the structure. Therefore, both the single chip structure and the multi chip structure are necessary for the heat management. It is necessary to establish an accurate and efficient three-dimensional heat transfer model. The main work of this paper is as follows: (1) the thermal resistance model is established on the basis of Friyege's conduction theory and the theory of thermal convection. By dividing the chip structure into several regions, the thermal resistance of each region is calculated, and the total heat resistance of X, y and Z is obtained, and the maximum temperature point and the average temperature of the boundary area are obtained. Because the expansion of the three-dimensional temperature is similar to the heat conduction of the ball wall, the temperature distribution between the nodes is calculated by the principle of the heat conduction of the ball wall. Finally, the basic theoretical model of the three-dimensional heat transfer thermal resistance network model is established, including the temperature model of the heat source center, the temperature distribution model and the iterative calculation method. Based on the basic theoretical model of three-dimensional heat transfer and thermal resistance network model, a single chip structure thermal resistance network model and a multilayer chip stack thermal resistance network model are obtained, and the corresponding thermal resistance analysis chart is made respectively. For the analysis of the convective heat resistance, an innovative method of iterative calculation is used to calculate the convective coefficient corresponding to the convective heat resistance. (2) correct 3D thermal network heat transfer model is verified by ANSYS simulation, the three-dimensional heat transfer thermal resistance network model calculated parameters as parameters of ANSYS modeling, the convection coefficient theory of three-dimensional thermal resistance network model calculated using power and iteration as the load of the ANSYS model, and the two data contrast verification. The results show that the temperature difference between the highest temperature point of the heat source center and the Ansys simulation result is less than 10% under different heating rate and heat source size, showing the accuracy of the three-dimensional heat transfer and thermal resistance network model. (3) through the experimental test of special resistance test chip, and the theory of three-dimensional thermal resistance network model test results and single chip structure by comparing calculation results and simulation results of ANSYS, get the error and error of ANSYS simulation and experimental test of 3D thermal network heat transfer model and experimental tests are less than 10%, the accuracy of 3D the thermal resistance network model is verified from the experimental point of view. (4) in order to improve work efficiency, computer aided analysis is applied to modeling and Simulation of thermal resistance network model of stacked structure. A thermal analysis software based on Windows platform is developed. The software takes VC++ as the main development tool. It has friendly interface, simple operation, good portability and high accuracy. It has a certain auxiliary role in thermal design of multilayer chip stacking structure. The three dimensional heat transfer and thermal resistance network model can be applied to single layer and multilayer chip structure, and the corresponding three-dimensional temperature distribution can be obtained quickly and effectively. The three-dimensional heat transfer and thermal resistance network model is verified by the experimental results of ANSYS simulation software and special thermal resistance test chip, and the correctness and effectiveness of the thermal resistance network model is proved. In the design of single-layer and multi-layer stacked chip structure, the 3D heat transfer thermal resistance network model has some reference value for thermal design.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TN40

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1 仝振陽;面向三維高密度集成系統(tǒng)的多物理場耦合算法的研究與開發(fā)[D];東南大學(xué);2016年

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本文編號：1347173