【摘要】：當(dāng)前,時(shí)鐘頻率和數(shù)據(jù)傳輸速率越來(lái)越高,PCB行業(yè)為了保持信號(hào)的完整性,對(duì)特性阻抗的控制正變得越來(lái)越嚴(yán)格,同時(shí),對(duì)于特性阻抗測(cè)試儀的帶寬、穩(wěn)定性和測(cè)量精度等指標(biāo)都提出了更高的要求,對(duì)于多功能和更加智能化的特性阻抗測(cè)試儀軟件的需求也更加迫切。本論文正是針對(duì)上述問(wèn)題,從特性阻抗測(cè)試儀的軟件關(guān)鍵技術(shù)入手,重點(diǎn)研究和實(shí)現(xiàn)了帶寬提升算法、時(shí)鐘抖動(dòng)算法、增強(qiáng)兩點(diǎn)校準(zhǔn)算法。本論文的具體研究?jī)?nèi)容如下：研究和實(shí)現(xiàn)了帶寬提升算法。首先分析了提升帶寬所使用的帶寬增強(qiáng)濾波技術(shù)和數(shù)字帶寬交插復(fù)用(DBI)技術(shù)及其優(yōu)缺點(diǎn),然后在此基礎(chǔ)上選擇了帶寬增強(qiáng)濾波技術(shù)作為實(shí)施方案。該方案是通過(guò)選擇性的“放大”信號(hào)的高頻成分,將儀器的-3dB點(diǎn)的頻率響應(yīng)提升到更高的頻率,從而提高儀器的帶寬,最終實(shí)現(xiàn)了帶寬由2.3GHz提升到2.97GHz,提高了儀器的分辨率。研究和實(shí)現(xiàn)了時(shí)鐘抖動(dòng)算法。通過(guò)討論時(shí)鐘抖動(dòng)的分析方法及其對(duì)信號(hào)采樣的影響,進(jìn)而實(shí)現(xiàn)了基于順序等效采樣的時(shí)鐘抖動(dòng)算法。該算法首先是根據(jù)采樣信號(hào)及其平均信號(hào)之間的關(guān)系,統(tǒng)計(jì)出時(shí)鐘抖動(dòng)的概率密度分布并根據(jù)Tailfit抖動(dòng)分離技術(shù)將總抖動(dòng)(TJ)分解為確定性抖動(dòng)(DJ)和隨機(jī)抖動(dòng)(RJ)兩部分,然后統(tǒng)計(jì)出周期抖動(dòng)(PJ)、周期間抖動(dòng)(CCJ)和時(shí)間間隔誤差(TIE)的峰峰值,最后以泰克TDSJTT3抖動(dòng)分析軟件的測(cè)試結(jié)果作為參照標(biāo)準(zhǔn),驗(yàn)證了該算法的有效性,從而為檢測(cè)儀器的穩(wěn)定性提供了定量的分析手段,并為后續(xù)硬件設(shè)計(jì)自校準(zhǔn)電路提供了基礎(chǔ)。研究和實(shí)現(xiàn)了增強(qiáng)兩點(diǎn)校準(zhǔn)算法。該算法是在兩點(diǎn)校準(zhǔn)算法的基礎(chǔ)上進(jìn)行改進(jìn)的,改進(jìn)的地方主要包括采用波形平均的方式減小特性阻抗測(cè)試過(guò)程中的隨機(jī)誤差；采用自動(dòng)選擇最佳測(cè)量區(qū)域的方式提高校準(zhǔn)精度；通過(guò)為每個(gè)通道配置獨(dú)立的校準(zhǔn)參數(shù)提高通道之間的獨(dú)立性和一致性。最后以泰克儀器的測(cè)試結(jié)果為參照標(biāo)準(zhǔn),驗(yàn)證了該算法可以有效的提高特性阻抗的測(cè)量精度。設(shè)計(jì)和實(shí)現(xiàn)了通道擴(kuò)展以及自適應(yīng)波形顯示功能。將原有軟件由2通道擴(kuò)展為4通道,并且使測(cè)量波形能夠根據(jù)被測(cè)物的實(shí)際情況自動(dòng)地調(diào)整以便完整的顯示在視圖區(qū)的最佳位置,從而使特性阻抗測(cè)試儀更加適應(yīng)大規(guī)模工業(yè)流水線(xiàn)混合智能化測(cè)試。本文的最后對(duì)軟件的功能、性能和異常情況進(jìn)行了測(cè)試并分析了測(cè)試結(jié)果。
[Abstract]:At present, in order to maintain the integrity of signal, the control of characteristic impedance is becoming more and more strict in the PCB industry with the increasing clock frequency and data transmission rate. At the same time, the bandwidth of the characteristic impedance tester is becoming more and more strict. The requirements of stability and measurement accuracy are higher, and the requirement of multi-function and more intelligent characteristic impedance tester software is more urgent. Aiming at the above problems, this paper starts with the key software technology of the characteristic impedance tester, and focuses on the research and implementation of bandwidth enhancement algorithm, clock jitter algorithm and enhanced two-point calibration algorithm. The main contents of this thesis are as follows: the bandwidth enhancement algorithm is studied and implemented. Firstly, the bandwidth enhancement filtering technology and digital bandwidth interleaved multiplexing (DBI) technology are analyzed, and then the bandwidth enhancement filtering technology is selected as the implementation scheme. By selectively "amplifying" the high-frequency component of the signal, the frequency response of -3dB point of the instrument is raised to a higher frequency, thus the bandwidth of the instrument is increased, and the bandwidth is raised from 2.3GHz to 2.97GHz, and the resolution of the instrument is improved. The clock jitter algorithm is studied and implemented. By discussing the analysis method of clock jitter and its influence on signal sampling, a clock jitter algorithm based on sequential equivalent sampling is implemented. Firstly, according to the relationship between the sampled signal and its average signal, the probability density distribution of clock jitter is calculated, and the total jitter (TJ) is decomposed into deterministic jitter (DJ) and random jitter (RJ) according to Tailfit jitter separation technique. Then the peak value of jitter (CCJ) and interval error (TIE) during the period jitter (PJ), cycle is calculated. Finally, the test results of Teke TDSJTT3 jitter analysis software are used as the reference standard to verify the validity of the algorithm. It provides a quantitative analysis method for the stability of the instrument and provides a basis for the subsequent hardware design of the self-calibrating circuit. An enhanced two-point calibration algorithm is studied and implemented. The algorithm is improved on the basis of two-point calibration algorithm. The improvement mainly includes using waveform averaging to reduce the random error in the process of characteristic impedance testing. The calibration accuracy is improved by automatically selecting the best measurement area, and the independence and consistency of each channel is improved by configuring independent calibration parameters for each channel. Finally, using the test results of the Tak instrument as the reference standard, it is verified that the algorithm can effectively improve the measurement accuracy of the characteristic impedance. The function of channel expansion and adaptive waveform display is designed and implemented. The original software is extended from 2 channels to 4 channels, and the measurement waveform can be automatically adjusted according to the actual situation of the object under test in order to display the best position in the view area. Thus, the characteristic impedance tester is more suitable for large scale industrial pipeline hybrid intelligent test. Finally, the function, performance and exception of the software are tested and the test results are analyzed.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類(lèi)號(hào)】：TM934.7

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

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本文編號(hào)：2235072