本文選題：低壓大電流 + 電壓調(diào)節(jié)模塊　； 參考：《西安電子科技大學(xué)》2014年碩士論文

【摘要】：電壓調(diào)節(jié)模塊(Voltage Regulator Module VRM)是用來為快速微處理器供電的DC/DC電源模塊。其發(fā)展趨勢為輸出低電壓、大電流、瞬態(tài)響應(yīng)快、電壓紋波小,電源體積小,工作頻率高,效率及可靠性高。論文基于VRM的技術(shù)發(fā)展和應(yīng)用要求,研究設(shè)計(jì)一款48V輸入、1.2V/150A輸出的電壓調(diào)節(jié)模塊。在微處理器對VRM性能需求分析的基礎(chǔ)上,論文確立設(shè)計(jì)的總體方案為:主電路采用“不對稱半橋+多相交錯(cuò)并聯(lián)SR-Buck”兩級式變換拓?fù)浣Y(jié)構(gòu),控制電路采用復(fù)合控制方式。前級主電路設(shè)計(jì)采用軟開關(guān)技術(shù),有效解決了高頻引起的開關(guān)損耗問題,減小電路損耗。后級主電路采用同步整流、交錯(cuò)并聯(lián)及并聯(lián)均流三種關(guān)鍵技術(shù)。引入同步整流技術(shù),減小輸出整流損耗;采用交錯(cuò)并聯(lián)技術(shù)減小輸出濾波電感、電容的容量,提高輸出的動(dòng)態(tài)響應(yīng)速度;應(yīng)用并聯(lián)均流技術(shù)解決交錯(cuò)并聯(lián)引起單元電路工作電流分布不均的問題,可有效提高變換器的可靠性。高頻變壓器設(shè)計(jì)方面,采用調(diào)節(jié)副邊繞組匝比來消除變壓器直流偏磁電流,有效解決變壓器正負(fù)伏秒積不平衡引起的直流偏磁現(xiàn)象。在對前、后級電路參數(shù)計(jì)算及控制電路設(shè)計(jì)基礎(chǔ)上,分別對前、后級設(shè)計(jì)電路應(yīng)用Saber和MATLAB/Simulink仿真軟件進(jìn)行建模與仿真,仿真結(jié)果驗(yàn)證理論分析正確性與設(shè)計(jì)方案的可行性。仿真表明:VRM輸出電壓為1.201V,電壓紋波系數(shù)為0.15%;總的輸出電流為150.01A,電流紋波系數(shù)為0.2%;效率高達(dá)89.7%;均滿足設(shè)計(jì)要求。
[Abstract]:Voltage regulator Module (VRM) is a DC / DC power supply module used to power a fast microprocessor. Its development trend is low output voltage, high current, fast transient response, small voltage ripple, small power supply volume, high working frequency, high efficiency and high reliability. Based on the technical development and application requirements of VRM, a 48V voltage regulation module with 1.2V / 150A output is designed. Based on the analysis of VRM performance requirement of microprocessor, the overall scheme of the design is as follows: the main circuit adopts the "asymmetrical half-bridge multi-phase parallel SR-Buck" two-stage transformation topology, and the control circuit adopts the compound control mode. The soft switching technology is used in the design of the front stage main circuit, which effectively solves the problem of switching loss caused by high frequency and reduces the circuit loss. The main circuit adopts three key technologies: synchronous rectifier, staggered parallel connection and parallel current sharing. The synchronous rectifier technology is introduced to reduce the output rectifier loss, the interleaving parallel connection technique is used to reduce the capacity of the output filter inductor and capacitance, and the dynamic response speed of the output is improved. The application of parallel current sharing technique to solve the problem of uneven distribution of working current caused by interleaving parallel connection can effectively improve the reliability of the converter. In the design of high frequency transformer, the DC bias current of transformer is eliminated by adjusting the turn ratio of secondary side winding, and the phenomenon of DC bias caused by unbalance of positive and negative volt second product of transformer is effectively solved. On the basis of parameter calculation and control circuit design of front and back stage circuit, the model and simulation of front and back stage design circuit are carried out by using Saber and MATLAB / Simulink simulation software respectively. The simulation results verify the correctness of theoretical analysis and the feasibility of the design scheme. The simulation results show that the output voltage of VRM is 1.201 V, the ripple coefficient of voltage is 0.15, the total output current is 150.01A, the coefficient of current ripple is 0.2, the efficiency is up to 89.7V, and all meet the design requirements.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TM46

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本文編號：2113164