本文選題：智能變電站 + 時鐘同步　； 參考：《大連理工大學》2015年碩士論文

【摘要】：近幾年國家電網(wǎng)大力建設堅強智能電網(wǎng),作為其構成基礎的智能變電站的作用也變得越來越重要。由于智能電網(wǎng)具有分布式的結構特點,需要自上而下保持動作的一致性和準確性,因此要求系統(tǒng)內(nèi)的智能變電站以及變電站中的設備運行需要在統(tǒng)一的時間基準之下。雖然現(xiàn)有的時鐘同步技術很多,但都不能在保證可靠運行和節(jié)約成本的前提下提高智能變電站的對時精度。IEEE1588精確時間同步協(xié)議的提出為智能變電站提供了一種全新的時鐘同步解決方案,依靠站中已存的通信網(wǎng)絡基礎可使全站實現(xiàn)亞微秒級同步精度。論文依據(jù)IEEE1588精確時間協(xié)議,設計了一套基于FPGA+DM9000+DP83640的時鐘同步系統(tǒng),用于解決智能變電站的同步問題。該系統(tǒng)既可以為主時鐘同步其它從時鐘,也可以為從時鐘與主時鐘同步。論文首先介紹IEEE1588協(xié)議的同步機制和相關原理,對主要的時鐘同步模型、PTP時鐘屬性、PTP報文及數(shù)據(jù)集作了相關闡述,在此基礎上,確定時鐘同步系統(tǒng)的整體框架。在硬件部分采用FPGA作為主控芯片完成相關程序和狀態(tài)機的維護；采用DM9000作為以太網(wǎng)控制器；采用DP83640作為物理層芯片使MII接口獨立,完成時間戳信息的加蓋和獲��；設計GPS模塊保證系統(tǒng)作為主時鐘的精確性和可靠性。軟件部分設計了PTP時鐘狀態(tài)機和最佳主時鐘算法,用于本地時鐘自主選擇其在PTP系統(tǒng)內(nèi)的主時鐘,保證PTP系統(tǒng)的穩(wěn)定運行；設計了報文處理程序,用于正確收發(fā)報文；設計了本地時鐘調(diào)節(jié)程序,當本地時鐘為從時鐘時,通過偏移量調(diào)節(jié)和頻率調(diào)節(jié)算法,完成與主時鐘的精確同步；同時設計了相關硬件的驅動程序,保證時鐘系統(tǒng)的穩(wěn)定運行。論文最后給出驗證方案,搭建IEEE1588時鐘同步系統(tǒng)同步精度測試平臺并實驗,根據(jù)采樣數(shù)據(jù)和輸出秒脈沖波形的分析證明該系統(tǒng)設計的合理性,其同步精度可滿足智能變電站的需求。
[Abstract]:In recent years, the State Grid has made great efforts to build a strong smart grid, and the role of intelligent substation, which is the basis of it, has become more and more important. Because the smart grid has the characteristic of distributed structure, it needs to keep the consistency and accuracy of the action from top to bottom, so it is required that the intelligent substation and the equipment in the substation operate under the unified time standard. Although there are a lot of clock synchronization techniques available, However, it is impossible to improve the timing accuracy of intelligent substation. IEEE1588 precise time synchronization protocol can not guarantee reliable operation and save cost, which provides a new solution for intelligent substation clock synchronization. Depending on the existing communication network, the sub-microsecond synchronization accuracy can be realized. According to IEEE1588 precise time protocol, a clock synchronization system based on FPGA DM9000 DP83640 is designed to solve the synchronization problem of intelligent substation. The system can synchronize the slave clock with the slave clock as well as the slave clock. This paper first introduces the synchronization mechanism and related principles of IEEE1588 protocol, and describes the main clock synchronization model: PTP clock attribute PTP message and data set. On this basis, it determines the overall framework of clock synchronization system. In the hardware part, FPGA is used as the main control chip to complete the maintenance of the related program and state machine, DM9000 is used as the Ethernet controller, DP83640 is used as the physical layer chip to make the Mii interface independent, and the timestamp information is stamped and obtained. GPS module is designed to ensure the accuracy and reliability of the system as the master clock. In the software part, the PTP clock state machine and the best master clock algorithm are designed, which can be used to select the master clock in the PTP system independently to ensure the stable operation of the PTP system, and the message processing program is designed to send and receive the message correctly. The local clock adjusting program is designed. When the local clock is slave clock, the accurate synchronization with the master clock is accomplished by offset adjustment and frequency adjustment algorithm. At the same time, the related hardware driver is designed to ensure the stable operation of the clock system. At the end of the paper, the verification scheme is given, and the synchronization precision test platform of IEEE1588 clock synchronization system is built and experimented. According to the analysis of sampling data and output second pulse waveform, the rationality of the system design is proved. Its synchronization accuracy can meet the needs of intelligent substation.
【學位授予單位】：大連理工大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN791;TM76

【參考文獻】

相關期刊論文 前3條

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本文編號：2072230