本文選題：電源管理芯片 + 恒定導(dǎo)通時間�。� 參考：《西安電子科技大學(xué)》2014年碩士論文

【摘要】：隨著電子技術(shù)的飛速發(fā)展,各式各樣的電子產(chǎn)品在我們的日常生活中已隨處可見,電源管理芯片作為電子產(chǎn)品的心臟,其性能的好壞直接決定著電子產(chǎn)品的續(xù)航時間和壽命。所以為了提高電子產(chǎn)品的性能,電源管理類芯片的研究與發(fā)展成為現(xiàn)代科技發(fā)展的一個重要課題。電源管理類芯片正在向著低功耗,低成本,面積小,高轉(zhuǎn)換效率的方向發(fā)展。在電源管理類芯片中,DC-DC開關(guān)型電源具有功耗低,轉(zhuǎn)換效率高,成本低的優(yōu)點,但是難以將整個系統(tǒng)集成在一個芯片中。近年來DC-DC開關(guān)型電源得到了廣泛使用,特別是在大功率的使用場合。本論文主要研究在BCD工藝下降壓型DC-DC電源管理芯片的設(shè)計、仿真與實現(xiàn)。論文從電特性指標(biāo)開始,到電路設(shè)計,再到電路性能仿真,設(shè)計了一款寬電壓輸入范圍,寬電壓輸出范圍和大電流輸出的Buck DC-DC電源管理類芯片。論文首先介紹了電源管理芯片的發(fā)展概況,以及電源芯片的研究意義,然后介紹了三種DC-DC(Buck,Boost和Buck/Boost)的拓?fù)浣Y(jié)構(gòu),并詳細(xì)介紹了降壓型DC-DC的基本工作原理,電壓�？刂婆c電流�？刂频膮^(qū)別,以及連續(xù)導(dǎo)通模式和不連續(xù)導(dǎo)通模式的工作原理,三種不同的降壓型DC-DC調(diào)制方式(脈沖寬度調(diào)制方式,脈沖頻率調(diào)制方式,混合調(diào)制方式)的區(qū)別,并對降壓型DC-DC的穩(wěn)定性及補(bǔ)償網(wǎng)絡(luò)參數(shù)設(shè)計進(jìn)行了詳細(xì)分析,為該芯片的設(shè)計和仿真實現(xiàn)提供了全面的準(zhǔn)備工作。本論文中的降壓型DC-DC電源管理芯片采用恒定導(dǎo)通時間控制,在重載時采用連續(xù)導(dǎo)通模式,輕載時可以強(qiáng)制為連續(xù)導(dǎo)通模式也可以工作非連續(xù)導(dǎo)通(DCM)模式,使其效率可以高達(dá)92%。該芯片實現(xiàn)了4.5V到28 V的寬輸入的電壓范圍,0.6 V到5 V的寬輸出的電壓范圍,采用電流�？刂�,使得該芯片有快速的瞬態(tài)響應(yīng)速度。芯片采用谷值電流模式控制方式,不管是在輕載還是在重載的情況下,該芯片都能夠?qū)崿F(xiàn)較高的效率轉(zhuǎn)換,由于該芯片采用的恒定導(dǎo)通時間和谷值電流模式的控制方式,使得在上一個周期產(chǎn)生的誤差信號帶不到下一個周期,所以即使在占空比大于%50的情況下也不會產(chǎn)生亞諧波振蕩,不需要斜坡補(bǔ)償電路。該芯片加入軟啟動電路,使誤差放大器的輸出comp端在上電啟動時緩慢上升,從而消除了上電時的浪涌電流。此外,芯片上還集成了短路保護(hù),過壓保護(hù)OV,欠壓保護(hù)UV等各種保護(hù)電路。本文研究的恒定導(dǎo)通時間和谷值電流檢測降壓型DC/DC轉(zhuǎn)換器芯片是基于0.35um BCD工藝設(shè)計,使用Cadence spectre軟件搭建芯片的各個電路模塊,并對單個模塊和整體電路進(jìn)行了設(shè)計和各個Corner的仿真,仿真結(jié)果表明單個模塊和整體電路的仿真結(jié)果滿足整體芯片的要求,具有良好的電壓調(diào)整率和負(fù)載調(diào)整率,效率可以達(dá)到92%。該芯片的整體電路已經(jīng)設(shè)計并仿真完成。
[Abstract]:With the rapid development of electronic technology, all kinds of electronic products have been widely seen in our daily life. As the heart of electronic products, the performance of power management chip directly determines the life and life of electronic products. Therefore, in order to improve the performance of electronic products, the research and development of power management chips has become an important subject in the development of modern science and technology. Power management chips are developing towards low power consumption, low cost, small area and high conversion efficiency. In the power management chip, DC-DC switching power supply has the advantages of low power consumption, high conversion efficiency and low cost, but it is difficult to integrate the whole system into one chip. In recent years, DC-DC switching power supply has been widely used, especially in high power applications. This paper mainly studies the design, simulation and realization of the power supply management chip of DC-DC in BCD process. In this paper, a Buck DC-DC power supply management chip with wide voltage input range, wide voltage output range and high current output is designed from electrical characteristic index to circuit design and circuit performance simulation. This paper first introduces the development of power management chip and the significance of power chip research, then introduces the topology of three DC-DC Buck boost and Buck / boost, and introduces the basic working principle of reduced voltage DC-DC in detail. The difference between voltage mode control and current mode control, as well as the working principle of continuous and discontinuous conduction mode, three different step-down DC-DC modulation modes (pulse width modulation, pulse frequency modulation), The stability of the DC-DC and the design of the compensation network parameters are analyzed in detail, which provides a comprehensive preparation for the design and simulation of the chip. In this paper, the step-down DC-DC power supply management chip adopts constant on-time control, continuous on-on mode at heavy load, and can be forced into continuous on-mode or discontinuous on-DCM mode at light load, making its efficiency as high as 92%. The wide input voltage range of 4.5V to 28V and the wide output voltage range of 0.6 V to 5V are realized in the chip. The current mode control is used to make the chip have a fast transient response speed. The chip adopts valley current mode control mode, whether in light load or heavy load, the chip can achieve high efficiency conversion, because of the constant on-time and valley current mode control mode. Because the error signal produced in the last period is less than the next period, there is no subharmonic oscillation even if the duty cycle is larger than P, and no ramp compensation circuit is needed. By adding soft start circuit, the output comp of the error amplifier rises slowly when the power is on, thus eliminating the surge current when the power is on. In addition, the chip also integrated short circuit protection, over-voltage protection OV, under-voltage protection UV and other protection circuits. The DC/DC converter chip of constant on-time and valley current detection in this paper is based on the 0.35um BCD process design. Each circuit module of the chip is built with Cadence spectre software. The single module and the whole circuit are designed and the simulation results of each Corner show that the simulation results of the single module and the whole circuit meet the requirements of the whole chip, and have good voltage adjustment rate and load adjustment rate. Efficiency can reach 92. The whole circuit of the chip has been designed and simulated.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TM46

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相關(guān)期刊論文 前1條

1 黃建剛;羅明;代高強(qiáng);周澤坤;明鑫;張波;;一種基于ACOT的高效降壓型DC/DC變換器[J];微電子學(xué);2013年04期

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本文編號：1968223