本文選題：RFID + 傳感器電子標(biāo)簽��； 參考：《復(fù)旦大學(xué)》2014年碩士論文

【摘要】：近年來(lái),電子標(biāo)簽與傳感器的結(jié)合成為射頻識(shí)別(RFID)技術(shù)的研究熱點(diǎn)之一。傳感器標(biāo)簽前端中的模擬模塊主要包含帶隙基準(zhǔn)、電源管理和上下電復(fù)位電路(POR)模塊。其中低壓差線性穩(wěn)壓器(LDO)結(jié)構(gòu)簡(jiǎn)單、面積小、功耗低,適合作為傳感器標(biāo)簽芯片中電源管理模塊,為電子標(biāo)簽和傳感器供電。設(shè)計(jì)此類(lèi)線性穩(wěn)壓器需要滿足寬范圍低電源電壓、低功耗條件下工作,因?yàn)闊o(wú)源標(biāo)簽的能量會(huì)隨著讀寫(xiě)距離的變化而變化,此外需要優(yōu)化LDO的電源電壓抑制(PSR)能力以及環(huán)路穩(wěn)定性。本文從低壓低功耗的方向?qū)鞲衅髑岸酥械哪M模塊進(jìn)行了研究,設(shè)計(jì)了一款符合傳感器電子標(biāo)簽應(yīng)用的LDO。文中重點(diǎn)設(shè)計(jì)了其中的Sub-1-V帶隙基準(zhǔn)(Bandgap)模塊,LDO模塊。針對(duì)應(yīng)用需求設(shè)計(jì)了POR模塊。本文以應(yīng)用背景為切入點(diǎn),研究分析了傳感器標(biāo)簽前端中的模擬電路設(shè)計(jì)難點(diǎn),并制訂了可行的設(shè)計(jì)指標(biāo)(SPEC)。其次介紹了LDO、Bandgap、POR電路工作原理,并針對(duì)每個(gè)模塊的設(shè)計(jì)指標(biāo)做優(yōu)化設(shè)計(jì),得到了最終的折衷方案。本文通過(guò)改進(jìn)低壓運(yùn)放(OTA)電路結(jié)構(gòu),從而滿足了超低壓帶隙基準(zhǔn)的電路設(shè)計(jì)。在0.13um標(biāo)準(zhǔn)CMOS工藝條件下,帶隙基準(zhǔn)的工作電壓范圍在全工藝角下是0.75V-1.6V,輸出參考電壓為600mV,低頻處的PSR約為64.5dB,在13.56MHz處的PSR約為60dB,靜態(tài)電流為2.5uA；文中設(shè)計(jì)的LDO(不包含Bandgap)的靜態(tài)功耗約為2.5uA,低頻處的PSR約為55dB,13.56MHz處PSR為60dB。POR復(fù)位延遲時(shí)間約為50us,靜態(tài)功耗小于200nA。文中的設(shè)計(jì)是借助cadence的spectre仿真器仿真,仿真結(jié)果表明符合設(shè)計(jì)預(yù)期,電路最終通過(guò)版圖后仿。
[Abstract]:In recent years, the combination of electronic tags and sensors has become one of the research hotspots in RFID technology. The analog module in the front end of sensor label mainly includes bandgap reference, power management and power reset circuit (POR) module. The low voltage difference linear regulator (LDO) is simple in structure, small in area and low in power consumption. It is suitable for the power management module in the sensor tag chip and the power supply for the electronic tag and sensor. The design of this type of linear regulator requires a wide range of low power supply voltages and low power consumption because the energy of the passive label varies with the read / write distance. In addition, the power supply voltage suppression capacity and loop stability of LDO need to be optimized. In this paper, the analog module in the front end of the sensor is studied in the direction of low voltage and low power consumption, and a LDO is designed for the sensor tag application. In this paper, the Sub-1-V bandgap reference module is designed. The POR module is designed to meet the application requirements. In this paper, based on the application background, the difficulties of analog circuit design in the front end of sensor label are studied and analyzed, and the feasible design index is worked out. Secondly, the working principle of LDO Bandgapa POR circuit is introduced, and the design index of each module is optimized, and the final compromise scheme is obtained. In this paper, the circuit design of ultra low voltage bandgap reference is satisfied by improving the circuit structure of low voltage operational amplifier (OTA). Under the condition of 0.13um standard CMOS process, The working voltage range of bandgap reference is 0.75V-1.6V, the output reference voltage is 600mV, the PSR at low frequency is about 64.5 dB, the PSR at 13.56MHz is about 60dB, and the static current is 2.5uA. The PSR is about 55 dB ~ 13.56 MHz PSR is 60dB.POR reset delay time is about 50 us. the static power consumption is less than 200 na. The design of this paper is based on the simulation of spectre simulator of cadence. The simulation results show that the circuit meets the design expectations and the circuit is simulated after layout.
【學(xué)位授予單位】：復(fù)旦大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類(lèi)號(hào)】：TM44

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本文編號(hào)：1944774