本文選題：LDO　切入點(diǎn)：無片外電容　出處：《湘潭大學(xué)》2014年碩士論文

【摘要】：近年來隨著便攜式電子產(chǎn)品的迅速普及，電源管理芯片需求急劇增加。電源管理的主要目的是提高功率器件的效率，從而延長電池壽命和設(shè)備的使用時(shí)間。作為電源管理芯片中最為常見的產(chǎn)品，低壓差線性穩(wěn)壓器，即LDO (low dropout regulator)，由于具有電路簡單，低噪聲及低功耗的優(yōu)點(diǎn)，因此獲得了廣泛的應(yīng)用。然而，，傳統(tǒng)的LDO需要外接片外大電容，這樣一方面增加了PCB (Printed Circuit Board)的面積；另一方面也增加了芯片的應(yīng)用成本，而且也難于在SOC (System on Chip)芯片中使用。因此，無片外電容LDO成為業(yè)界關(guān)注的熱點(diǎn)。 無片外電容LDO的設(shè)計(jì)存在兩個(gè)難點(diǎn)。首先，傳統(tǒng)LDO環(huán)路主極點(diǎn)位于輸出節(jié)點(diǎn)，利用外接大電容的等效電阻產(chǎn)生一個(gè)左半平面零點(diǎn)進(jìn)行頻率補(bǔ)償，而無片外電容LDO的環(huán)路穩(wěn)定性就必須重新考慮。其次，當(dāng)LDO的負(fù)載電流發(fā)生瞬態(tài)跳變時(shí)，傳統(tǒng)LDO主要利用片外電容進(jìn)行充放電，以減小輸出電壓的過沖和尖峰。但對(duì)于無片外電容LDO，就必須通過提高環(huán)路的響應(yīng)速度來提高瞬態(tài)響應(yīng)速度，但單純提高帶寬會(huì)導(dǎo)致電路功耗的增加。因此，業(yè)界通常會(huì)設(shè)計(jì)一個(gè)擺率增強(qiáng)模塊，在負(fù)載電流突變時(shí)大幅度增加誤差放大器的擺率，以提高LDO的瞬態(tài)響應(yīng)速度；而在正常供電時(shí)，擺率增強(qiáng)模塊不工作，以節(jié)省功耗。本文首先在這兩個(gè)方面做了深入調(diào)研，對(duì)前人提出的結(jié)構(gòu)和電路進(jìn)行討論分析，在此基礎(chǔ)上提出了新的電路結(jié)構(gòu)。 本論文所設(shè)計(jì)的低功耗無片外電容LDO用于為一款低功耗SIGMA-DELTA ADC中的數(shù)字電路供電。電路基于MXIC0.35μm標(biāo)準(zhǔn)CMOS工藝實(shí)現(xiàn)，設(shè)計(jì)輸出電壓3.3V，最大負(fù)載電流5mA，電源電壓在2.7V~5.5V之間變化。整體電路分為帶隙基準(zhǔn)源和LDO主體電路兩部分，帶隙基準(zhǔn)源為LDO提供一個(gè)與溫度及電源無關(guān)的參考電壓。其中帶隙基準(zhǔn)源為低功耗結(jié)構(gòu)，電流消耗僅為12μA。LDO主體電路中設(shè)計(jì)了一個(gè)擺率增強(qiáng)模塊，可以大大增加負(fù)載電流瞬態(tài)突變時(shí)誤差放大器的擺率，有效提高了LDO的瞬態(tài)響應(yīng)速度，從而降低了輸出電壓的尖峰和過沖。與相關(guān)文獻(xiàn)中的LDO相比，本文設(shè)計(jì)的LDO其擺率增強(qiáng)模塊具有結(jié)構(gòu)簡單，性能良好的特點(diǎn)。另外，通過將誤差放大器偏置在亞閾值區(qū)，有效降低了整體電路的功耗。通過利用CADENCE仿真驗(yàn)證，本文設(shè)計(jì)的LDO壓差電壓低于100mV，LDO電路的電流消耗為31μA，負(fù)載電流瞬態(tài)突變時(shí)輸出電壓尖峰小于100mV，滿足應(yīng)用要求。
[Abstract]:In recent years, with the rapid popularization of portable electronic products, the demand for power management chips has increased dramatically. The main purpose of power management is to improve the efficiency of power devices. As the most common product in the power management chip, the low-voltage differential linear regulator, that is, the LDO low dropout regulator, has the advantages of simple circuit, low noise and low power consumption. However, the traditional LDO requires large external capacitors, which not only increase the area of PCB printed Circuit Board.On the other hand, it also increases the application cost of the chip. It is also difficult to use in SOC system on Chip chips. Therefore, off-chip capacitive LDO has become a hot spot in the industry. There are two difficulties in the design of out-of-chip capacitance LDO. Firstly, the main pole of the traditional LDO loop is located at the output node, and the equivalent resistor of the external large capacitance is used to generate a left half plane zero point to compensate the frequency. However, the loop stability of LDO without off-chip capacitance must be reconsidered. Secondly, when the load current of LDO is transient jump, the traditional LDO mainly uses off-chip capacitance to charge and discharge. In order to reduce the overshoot and spike of the output voltage, the transient response speed must be improved by increasing the response speed of the loop without the out-of-chip capacitance LDO, but the increase of the bandwidth alone will lead to the increase of the power consumption of the circuit. The industry usually designs a pendulum enhancement module to dramatically increase the swing rate of the error amplifier in the event of a sudden change in load current to improve the transient response speed of the LDO, while under normal power supply, the pendulum enhancement module does not work. In order to save power consumption, this paper first makes a thorough investigation in these two aspects, discusses and analyzes the structure and circuit proposed by the predecessors, and then puts forward a new circuit structure. The low power off-chip capacitor LDO designed in this paper is used to supply power to a digital circuit in a low-power SIGMA-DELTA ADC. The circuit is implemented on the basis of MXIC0.35 渭 m standard CMOS process. The output voltage is 3.3 V, the maximum load current is 5 Ma, and the power supply voltage varies between 2.7V~5.5V. The whole circuit is divided into two parts: bandgap reference source and LDO main circuit. The bandgap reference source provides a reference voltage independent of temperature and power supply for LDO. The bandgap reference source is a low-power structure, and the current consumption is only 12 渭 A.LDO. A pendulum enhancement module is designed in the main circuit of 12 渭 A.LDO. It can greatly increase the swing rate of the error amplifier when the load current is transient abrupt, and improve the transient response speed of the LDO effectively, thus reducing the peak and overshoot of the output voltage. Compared with the LDO in the related literature, The pendulum enhancement module designed in this paper has the characteristics of simple structure and good performance. In addition, the power consumption of the whole circuit is effectively reduced by biasing error amplifier in the sub-threshold region. The current consumption of the designed LDO circuit is 31 渭 A, and the peak of output voltage is less than 100mV when the load current is transient abrupt, which meets the requirement of application.
【學(xué)位授予單位】：湘潭大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TM44

【參考文獻(xiàn)】

相關(guān)期刊論文 前2條

1 陳東坡;何樂年;嚴(yán)曉浪;;一種低靜態(tài)電流、高穩(wěn)定性的LDO線性穩(wěn)壓器[J];電子與信息學(xué)報(bào);2006年08期

2 鄒志革;楊詩洋;鄒雪城;雷擰銘;陳曉飛;余國義;;基于阻尼系數(shù)控制頻率補(bǔ)償?shù)臒o電容型LDO設(shè)計(jì)[J];微電子學(xué)與計(jì)算機(jī);2009年07期

本文編號(hào)：1653026