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一種恒流模式高級(jí)多功能集成負(fù)載開關(guān)的設(shè)計(jì)

發(fā)布時(shí)間:2018-03-13 02:12

  本文選題:電源路徑管理 切入點(diǎn):開關(guān)通路 出處:《復(fù)旦大學(xué)》2014年碩士論文 論文類型:學(xué)位論文


【摘要】:近年來(lái),基于電池供電系統(tǒng)和USB兼容供電系統(tǒng)的便攜式電子產(chǎn)品發(fā)展勢(shì)頭非常強(qiáng)勁。但是由于電池技術(shù)發(fā)展比較緩慢,USB驅(qū)動(dòng)負(fù)載能力受限,以及越來(lái)越多的子系統(tǒng)需要分時(shí)供電,傳統(tǒng)的PMIC的供電通道數(shù)量以及供電的質(zhì)量已經(jīng)不能夠滿足現(xiàn)代消費(fèi)類電子產(chǎn)品中對(duì)供電資源進(jìn)行有效管理和高效率利用的需求。因此,電源路徑管理中開關(guān)通路的設(shè)計(jì)變得尤為重要,其中高級(jí)多功能負(fù)載開關(guān)由于自身集成的保護(hù)功能齊全,靜態(tài)功耗低,物理尺寸小以及配置靈活而被廣泛應(yīng)用于便攜式電子產(chǎn)品的電源管理解決方案中。本文研究和設(shè)計(jì)了一款基于混合信號(hào)硅基互補(bǔ)氧化物(Complementary Metal-oxide Silicon, CMOS)工藝的,用于便攜式電子產(chǎn)品中電源通路管理的高級(jí)多功能集成負(fù)載開關(guān)芯片。論文的研究和設(shè)計(jì)圍繞低功耗、低成本、高精度、保護(hù)性能齊全以及具有簡(jiǎn)單方便可測(cè)試性等方面展開,從前期的系統(tǒng)定義、電路設(shè)計(jì)、仿真驗(yàn)證,到后期的版圖設(shè)計(jì)以及芯片測(cè)試,完整的實(shí)現(xiàn)并測(cè)試了了所設(shè)計(jì)的芯片。由于需要實(shí)現(xiàn)低功耗,設(shè)計(jì)中避免了使用冗余的電路模塊,使用中的電路模塊也盡可能少的消耗電流,夠用即可。出于成本的考慮,電路設(shè)計(jì)中盡可能的使用基于基本版圖層次的元器件,避免使用需要額外制作層次的元器件,比如NPN型三極管可以用基于CMOS工藝的PNP型三極管來(lái)實(shí)現(xiàn)。由于需要實(shí)現(xiàn)高精度的過流保護(hù),設(shè)計(jì)中采用了多處修調(diào)技術(shù)來(lái)完成這一指標(biāo)。因?yàn)楦呒啥、多功能是?fù)載開關(guān)的發(fā)展趨勢(shì),所以本設(shè)計(jì)中除了集成軟啟動(dòng)浪涌電流保護(hù)、過溫欠壓鎖定、可調(diào)恒流限流輸出、自動(dòng)重啟以外,還設(shè)計(jì)了反向電流阻斷保護(hù)的功能,并使其無(wú)關(guān)于功率開關(guān)管是導(dǎo)通狀態(tài)還是截止?fàn)顟B(tài)。由于測(cè)試成本在整個(gè)集成電路芯片開發(fā)中的比重非常高,因此論文所設(shè)計(jì)的芯片中集成了一種可以簡(jiǎn)單方便進(jìn)行芯片級(jí)篩選測(cè)試和封裝后成品測(cè)試的測(cè)試模式,涵蓋了幾乎所有的基本電路模塊性能測(cè)試,方便了測(cè)試糾錯(cuò)。
[Abstract]:In recent years, portable electronic products based on battery power supply system and USB compatible power supply system are developing very strongly. However, due to the slow development of battery technology, the capacity of USB driver is limited. As more and more subsystems need time-sharing power supply, the quantity of power supply channels and the quality of power supply of traditional PMIC can not meet the demand of effective management and efficient utilization of power supply resources in modern consumer electronic products. The design of switch path in power path management has become particularly important, among which the advanced multifunctional load switch has low static power consumption due to its integrated protection functions. Small physical size and flexible configuration are widely used in power management solutions for portable electronic products. This paper studies and designs a hybrid Si-based complementary Metal-oxide Silicon (CMOS) process. Advanced multifunctional integrated load switch chip for power path management in portable electronic products. The research and design of this paper focus on the aspects of low power consumption, low cost, high precision, complete protection performance, simple and convenient testability, etc. From the previous system definition, circuit design, simulation verification, layout design and chip test, the designed chip is implemented and tested. Because of the need to achieve low power consumption, redundant circuit modules are avoided in the design. Circuit modules in use also consume as little current as possible, enough. For cost reasons, use components based on the basic layout level as much as possible in circuit design, avoiding the use of components that require additional layers of fabrication. For example, NPN Triode can be realized by using PNP Triode based on CMOS process. Because of the need to realize high precision overcurrent protection, the design adopts multi-place modification technology to accomplish this target, because of the high integration level, Multifunction is the development trend of load switch, so in this design, in addition to integrating soft start surge current protection, over-temperature and under-voltage locking, adjustable constant current current limiting output, automatic restart, the function of reverse current blocking protection is also designed. And makes it irrelevant to whether the power switch is on or off. Because the test cost is very high in the whole IC chip development, Therefore, the chip designed in this paper integrates a test mode which can be easily used for chip-level screening test and packaged product test, which covers almost all the basic circuit module performance tests and facilitates the test error correction.
【學(xué)位授予單位】:復(fù)旦大學(xué)
【學(xué)位級(jí)別】:碩士
【學(xué)位授予年份】:2014
【分類號(hào)】:TM564

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本文編號(hào):1604345

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