本文選題：實時信號分析儀　切入點：PXI　出處：《電子科技大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：實時信號分析儀是無線通信、航空、導(dǎo)航等領(lǐng)域中廣泛使用的一種測試儀器。數(shù)字化、寬頻帶、高分辨率已成為實時信號分析儀的發(fā)展趨勢,這要求數(shù)據(jù)總線具備高傳輸帶寬,高穩(wěn)定性和可靠性。PXIE(面向儀器的PCIE總線擴展)是現(xiàn)在主流的儀器總線技術(shù),PCI Express v2.0達到5.0Gb/s的傳輸速率,PCIE差分串行傳輸和糾錯機制有力的保證了數(shù)據(jù)傳輸?shù)馁|(zhì)量。本文采用PXIE來實現(xiàn)實時信號分析儀中大量數(shù)據(jù)的高速穩(wěn)健傳輸。要完成設(shè)計首先需要對PXIE硬件規(guī)范和PCIE傳輸協(xié)議作深入的理解;再通過需求分析,給出PXIE高速接口的總體方案設(shè)計,并結(jié)合PXIE總線的實現(xiàn)方式,設(shè)計以FPGA為主體器件的詳細(xì)硬件實現(xiàn)方案,以及為實現(xiàn)數(shù)據(jù)高速傳輸,確立了PXIE傳輸協(xié)議、DMA控制器和高速緩存的邏輯設(shè)計方案;然后根據(jù)硬件實現(xiàn)方案,使用Cadence軟件作了詳細(xì)電路圖設(shè)計,設(shè)計的主要考慮因素是系統(tǒng)性能、功耗和集成度;最后根據(jù)邏輯設(shè)計方案,使用ISE14.2綜合開發(fā)平臺完成PXIE傳輸協(xié)議、DMA控制器和高速緩存的各模塊詳細(xì)邏輯設(shè)計和RTL級代碼編寫。其中DMA控制器和高速緩存的邏輯設(shè)計是本文重中之重。本文實現(xiàn)了PIO、DMA和中斷這三種數(shù)據(jù)傳輸方式。使用FIFO、RAM和DDR3這三種方式來完成不同類數(shù)據(jù)的緩存。在板卡硬件調(diào)試完成后,搭建FPGA邏輯調(diào)試平臺,對邏輯設(shè)計部分使用Xilinx ISE14.2綜合開發(fā)平臺自帶的Chipscope軟件進行在線調(diào)試驗證,主要包括高速接口的PIO功能、DMA功能、中斷功能。DMA讀傳輸速率達到5.78Gb/s,DMA寫的傳輸速率達到13.33 Gb/s,中斷信號工作正常,調(diào)試驗證結(jié)果與設(shè)計指標(biāo)相符,達到預(yù)期性能,表明方案設(shè)計、硬件電路和FPGA邏輯的正確性。本文高速接口硬件和邏輯設(shè)計已成功應(yīng)用于信號分析儀中。
[Abstract]:Real-time signal analyzer is a kind of testing instrument widely used in wireless communication, aviation, navigation and other fields. Digitization, wide band and high resolution have become the development trend of real-time signal analyzer, which requires the data bus to have high transmission bandwidth. High stability and reliability. PXIE. is the mainstream instrument bus technology. PCI Express v2.0 achieves the transmission rate of 5.0 GB / s. PCIE differential serial transmission and error correction mechanism can guarantee the quality of data transmission. In this paper, PXIE is used to realize the high speed and robust transmission of a large amount of data in the real-time signal analyzer. In order to complete the design, it is necessary to have a deep understanding of the PXIE hardware specification and the PCIE transmission protocol. Then through the requirement analysis, the overall scheme design of PXIE high-speed interface is given, and combining with the realization mode of PXIE bus, the detailed hardware implementation scheme with FPGA as the main device is designed, and in order to realize the high speed data transmission, The logic design scheme of PXIE transmission protocol and cache is established, and then the detailed circuit diagram is designed by using Cadence software according to the hardware implementation scheme. The main factors of the design are system performance, power consumption and integration. Finally, according to the logical design scheme, The ISE14.2 integrated development platform is used to complete the detailed logic design of each module of PXIE transport protocol controller and cache and the coding of RTL level code. Among them, the logical design of DMA controller and cache is the most important part of this paper. There are three kinds of data transmission modes: PIOODMA and interrupt. We use FIFO RAM and DDR3 to cache different kinds of data. After the hardware debugging of the board is finished, The FPGA logic debugging platform is built, and the online debugging and verification of the Chipscope software which is included in the Xilinx ISE14.2 integrated development platform is carried out in the logic design part, which mainly includes the PIO function of the high-speed interface. The interrupt function .DMA read transmission rate reached 5.78 GB / s / s, the transmission rate reached 13.33 GB / s, the interrupt signal worked normally, the debugging and verification results were in line with the design index, and the expected performance was achieved, which indicated that the scheme was designed. The hardware and logic design of high speed interface in this paper has been successfully applied to signal analyzer.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TM935
，

本文編號：1584937