應(yīng)用于數(shù)字DC-DC中的ADC的研究與設(shè)計(jì)
發(fā)布時(shí)間：2018-09-19 17:25
【摘要】：隨著微電子技術(shù)的發(fā)展,電子設(shè)備中集成電路對(duì)電源的要求越來越高,數(shù)字電源管理芯片成為研究者關(guān)注的熱點(diǎn)。模數(shù)轉(zhuǎn)換器(Analog to Digital Convert,ADC)作為關(guān)鍵電路模塊,決定了數(shù)字DC-DC輸出電壓的性能,對(duì)滿足數(shù)字DC-DC性能要求的ADC進(jìn)行研究,具有重要意義。通過對(duì)擬實(shí)現(xiàn)數(shù)字DC-DC性能指標(biāo)的分析,根據(jù)其需要量化的模擬量輸入范圍窄、絕對(duì)精度要求高的特點(diǎn),實(shí)現(xiàn)了一款窗口型Flash ADC。首先,分析了傳統(tǒng)Flash ADC的結(jié)構(gòu),針對(duì)BUCK型數(shù)字DC-DC特性的要求,確定了本論文ADC的設(shè)計(jì)指標(biāo)和系統(tǒng)結(jié)構(gòu),為了減小電路規(guī)模,采用將預(yù)放大運(yùn)算前置的結(jié)構(gòu);其次,采用SMIC180nm的工藝,通過Spectre+matlab仿真器,完成了包括預(yù)放大電路、反饋運(yùn)放、比較器和編碼模塊的窗口型FlashADC的電路設(shè)計(jì)和各工藝角仿真。通過設(shè)置合理的參數(shù)和共模輸入電壓,在輸入電壓變化幅值為25.6mV時(shí),用4-bit ADC實(shí)現(xiàn)了最低有效位(LSB)為1.6mV的高絕對(duì)精度;再次,針對(duì)預(yù)放大電路中存在的失調(diào)會(huì)對(duì)電路產(chǎn)生較大影響的問題,深入研究了預(yù)放大電路的失調(diào)消除方法。通過對(duì)MOS晶體管襯底偏壓與其閾值電壓之間關(guān)系的仿真分析,發(fā)現(xiàn)合理調(diào)節(jié)襯底偏壓,可以改變MOS管的閾值電壓,進(jìn)而達(dá)到消除失調(diào)的目的。設(shè)計(jì)中將預(yù)放大電路的運(yùn)算放大器輸入對(duì)管設(shè)計(jì)在兩個(gè)獨(dú)立的阱中,以便獨(dú)立調(diào)節(jié)它們的襯底偏壓,數(shù)字信號(hào)控制著電阻分壓網(wǎng)絡(luò)輸出端的襯底電壓,當(dāng)預(yù)放大電路出現(xiàn)失調(diào)時(shí),在數(shù)字信號(hào)控制下通過逐次逼近的方法調(diào)節(jié)輸入對(duì)管的相對(duì)襯底偏壓,直至輸入對(duì)管等效閾值相等,失調(diào)得到消除,校準(zhǔn)結(jié)束。將具有失調(diào)電壓消除作用的預(yù)放大器應(yīng)用于設(shè)計(jì)的窗口型FlashADC中,可有效消除電路的失調(diào)。在完成整體系統(tǒng)設(shè)計(jì)仿真的基礎(chǔ)上,完成了 FlashADC的版圖設(shè)計(jì)及后仿真。結(jié)果表明,在工作電壓為3.3V,采樣頻率為15MHz的條件下,通過在輸入端引入失調(diào)電壓,然后使用本文提出的失調(diào)電壓消除方法進(jìn)行校正。仿真結(jié)果表明,在不采用失調(diào)消除技術(shù)時(shí),有效位數(shù)只能達(dá)到3.208-bit,而在采用失調(diào)消除技術(shù)之后,有效位數(shù)可以達(dá)到3.793-bit, SNDR為24.592dB,相較理想值25.84dB損失很小,滿足設(shè)計(jì)要求。
[Abstract]:With the development of microelectronics technology, the demand of integrated circuits for power supply in electronic equipment is becoming higher and higher. Digital power management chip has become a hot spot of researchers. As a key circuit module, analog-to-digital converter (Analog to Digital Convert,ADC) determines the output voltage performance of digital DC-DC. It is of great significance to study the ADC that meets the performance requirements of digital DC-DC. Based on the analysis of the performance index of digital DC-DC, a window type Flash ADC. is realized according to the characteristics of narrow input range and high absolute precision of analog quantity which needs to be quantified. Firstly, the structure of traditional Flash ADC is analyzed. According to the requirements of BUCK type digital DC-DC, the design index and system structure of this paper ADC are determined. In order to reduce the scale of the circuit, the preamplifier structure is adopted. Using SMIC180nm process and Spectre matlab simulator, the circuit design and process angle simulation of window type FlashADC including preamplifier circuit, feedback operational amplifier, comparator and coding module are completed. By setting reasonable parameters and common-mode input voltage, when the amplitude of input voltage is 25.6mV, the high absolute precision of 1.6mV with the lowest effective bit (LSB) is realized by 4-bit ADC. Aiming at the problem that the misadjustment in preamplifier circuit will have a great influence on the circuit, the method of eliminating the misadjustment of preamplifier circuit is studied in detail. Through the simulation analysis of the relationship between substrate bias voltage and threshold voltage of MOS transistor, it is found that the threshold voltage of MOS transistor can be changed by adjusting the substrate bias voltage reasonably, and the misalignment can be eliminated. In the design, the operational amplifier input pair of the preamplifier circuit is designed in two separate wells to adjust their substrate bias voltage independently, and the digital signal controls the substrate voltage at the output end of the resistive partial voltage network. When the preamplifier circuit is misaligned, the relative substrate bias of the input to the tube is adjusted by successive approximation under the control of the digital signal, until the equivalent threshold of the input to the tube is equal, the offset is eliminated, and the calibration is completed. The misalignment of the circuit can be effectively eliminated by applying the preamplifier with offset voltage elimination to the window type FlashADC. On the basis of the overall system design and simulation, the layout design and post-simulation of FlashADC are completed. The results show that when the operating voltage is 3.3 V and the sampling frequency is 15MHz, the offset voltage is introduced into the input and then corrected by using the offset voltage elimination method proposed in this paper. The simulation results show that the effective bit number can reach 3.208-bit without the offset elimination technique, and the effective bit number can reach 3.793-bit and SNDR is 24.592dB, which is less than the ideal 25.84dB loss and meets the design requirements.
【學(xué)位授予單位】：西安理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN792;TM46
本文編號(hào)：2250810
[Abstract]:With the development of microelectronics technology, the demand of integrated circuits for power supply in electronic equipment is becoming higher and higher. Digital power management chip has become a hot spot of researchers. As a key circuit module, analog-to-digital converter (Analog to Digital Convert,ADC) determines the output voltage performance of digital DC-DC. It is of great significance to study the ADC that meets the performance requirements of digital DC-DC. Based on the analysis of the performance index of digital DC-DC, a window type Flash ADC. is realized according to the characteristics of narrow input range and high absolute precision of analog quantity which needs to be quantified. Firstly, the structure of traditional Flash ADC is analyzed. According to the requirements of BUCK type digital DC-DC, the design index and system structure of this paper ADC are determined. In order to reduce the scale of the circuit, the preamplifier structure is adopted. Using SMIC180nm process and Spectre matlab simulator, the circuit design and process angle simulation of window type FlashADC including preamplifier circuit, feedback operational amplifier, comparator and coding module are completed. By setting reasonable parameters and common-mode input voltage, when the amplitude of input voltage is 25.6mV, the high absolute precision of 1.6mV with the lowest effective bit (LSB) is realized by 4-bit ADC. Aiming at the problem that the misadjustment in preamplifier circuit will have a great influence on the circuit, the method of eliminating the misadjustment of preamplifier circuit is studied in detail. Through the simulation analysis of the relationship between substrate bias voltage and threshold voltage of MOS transistor, it is found that the threshold voltage of MOS transistor can be changed by adjusting the substrate bias voltage reasonably, and the misalignment can be eliminated. In the design, the operational amplifier input pair of the preamplifier circuit is designed in two separate wells to adjust their substrate bias voltage independently, and the digital signal controls the substrate voltage at the output end of the resistive partial voltage network. When the preamplifier circuit is misaligned, the relative substrate bias of the input to the tube is adjusted by successive approximation under the control of the digital signal, until the equivalent threshold of the input to the tube is equal, the offset is eliminated, and the calibration is completed. The misalignment of the circuit can be effectively eliminated by applying the preamplifier with offset voltage elimination to the window type FlashADC. On the basis of the overall system design and simulation, the layout design and post-simulation of FlashADC are completed. The results show that when the operating voltage is 3.3 V and the sampling frequency is 15MHz, the offset voltage is introduced into the input and then corrected by using the offset voltage elimination method proposed in this paper. The simulation results show that the effective bit number can reach 3.208-bit without the offset elimination technique, and the effective bit number can reach 3.793-bit and SNDR is 24.592dB, which is less than the ideal 25.84dB loss and meets the design requirements.
【學(xué)位授予單位】：西安理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN792;TM46
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