本文選題：靜電放電(ESD) + TCAD仿真��； 參考：《中國科學(xué)技術(shù)大學(xué)》2017年碩士論文

【摘要】：隨著便攜式電子產(chǎn)品的發(fā)展和增多,其對電源的需求也越來越高,提高電源管理芯片的效率是設(shè)計(jì)中需要考量的關(guān)鍵因素之一;同時,隨著半導(dǎo)體工藝的進(jìn)步,靜電放電(ESD,Electrostatic Discharge)現(xiàn)象對芯片的危害日益嚴(yán)重。在電源管理芯片設(shè)計(jì)的過程中,研究相應(yīng)的片上ESD防護(hù)器件及電路,增強(qiáng)全芯片靜電防護(hù)能力也是非常重要的。本文基于華潤上華0.5 μ m BCD工藝,對ESD防護(hù)器件進(jìn)行研究設(shè)計(jì)及流片驗(yàn)證。利用TCAD軟件Silvaco仿真平臺,對比傳輸線脈沖(TLP,Transmission Line Pulse)測試結(jié)果進(jìn)行仿真擬合;基于Smic 0.13μm CMOS工藝進(jìn)行DC-DC轉(zhuǎn)換器的電路設(shè)計(jì)和前仿。研究內(nèi)容主要包括:1.研究ESD物理機(jī)制及器件仿真所用的物理模型。分析關(guān)鍵模型參數(shù)對ESD器件仿真結(jié)果的影響,主要包括摻雜濃度對觸發(fā)電壓的影響、結(jié)寬對維持電壓的影響和載流子壽命對維持電壓的影響等。通過對器件仿真中物理模型參數(shù)的調(diào)整,實(shí)現(xiàn)對MOS器件、可控硅(SCR,Silicon Controlled Rectifier)器件觸發(fā)電壓和維持電壓的校準(zhǔn)。使用同一組參數(shù)對以上共五個器件進(jìn)行仿真,并與TLP測試結(jié)果比較,使觸發(fā)電壓與維持電壓的相對誤差控制在10%以內(nèi)。然后運(yùn)用仿真得到的物理模型參數(shù)對四個雙向SCR器件進(jìn)行仿真預(yù)測,并與TLP測試進(jìn)行比較。2.通過研究和設(shè)計(jì)新型的ESD防護(hù)結(jié)構(gòu),改進(jìn)其ESD耐壓值和魯棒性。分別進(jìn)行了雙向SCR結(jié)構(gòu)的設(shè)計(jì)和創(chuàng)新以及保護(hù)環(huán)版圖結(jié)構(gòu)的研究和改進(jìn)。并且進(jìn)行了 Silvaco平臺的Atlas仿真分析,流片驗(yàn)證以及TLP測試。測試結(jié)果表明改進(jìn)后的結(jié)構(gòu)可以有效改善ESD防護(hù)器件的耐壓能力和魯棒性。3.研究和設(shè)計(jì)降壓型DC-DC轉(zhuǎn)換器環(huán)路,依據(jù)電壓模式,采用脈沖寬度調(diào)制的控制方式實(shí)現(xiàn)了從3.3V到1.2V的電壓轉(zhuǎn)化,其工作頻率為1MHz。其中整個環(huán)路主要包含主電路、誤差放大器、鋸齒波發(fā)生器、比較器、死區(qū)控制及驅(qū)動電路、電平轉(zhuǎn)換電路、電流檢測電路、邏輯控制電路這幾個模塊。4.在控制環(huán)路中加入電流檢測模塊和邏輯控制電路,從而改善DC-DC轉(zhuǎn)換器在負(fù)載電流變小時轉(zhuǎn)換效率大幅降低的問題。通過分裂晶體管的方法并進(jìn)行自動調(diào)整,減少小負(fù)載電流時工作的晶體管個數(shù),從而降低功耗,提高效率。四組仿真結(jié)果顯示,在20-500mA的寬負(fù)載范圍內(nèi),采用分裂晶體管的方法之后可以將效率提高到850%以上。
[Abstract]:With the development and increase of portable electronic products, the demand for power supply is becoming higher and higher. Improving the efficiency of power management chip is one of the key factors to be considered in the design; at the same time, with the progress of semiconductor technology,Electrostatic discharge (ESD) electrostatic discharge (ESD) phenomenon is becoming more and more harmful to chips.In the process of designing the power management chip, it is also very important to study the corresponding ESD protective devices and circuits on the chip and enhance the full chip electrostatic protection capability.In this paper, the design and verification of ESD protective devices are carried out based on China Resources BCD process of 0.5 渭 m.Using TCAD software Silvaco simulation platform, comparing the test results of transmission line pulse transmission Line Pulse.The circuit design and pre-simulation of DC-DC converter based on Smic 0.13 渭 m CMOS technology are carried out.The main contents of the study include: 1.The physical mechanism of ESD and the physical model used in device simulation are studied.The influence of the key model parameters on the simulation results of ESD devices is analyzed, including the influence of doping concentration on the trigger voltage, the effect of junction width on the maintenance voltage, and the influence of carrier lifetime on the maintenance voltage.By adjusting the parameters of physical model in device simulation, the trigger voltage and maintenance voltage of MOS device, SCR device and SCR Controlled Rectifier device are calibrated.The above five devices are simulated with the same set of parameters, and compared with the TLP test results, the relative error between the trigger voltage and the maintenance voltage is controlled within 10%.Then the four bidirectional SCR devices are simulated and predicted by the physical model parameters obtained by simulation, and compared with the TLP test. 2.By studying and designing a new type of ESD protection structure, its ESD voltage resistance and robustness are improved.The design and innovation of the bidirectional SCR structure and the research and improvement of the protective ring layout structure are carried out respectively.Atlas simulation analysis, stream verification and TLP test of Silvaco platform are also carried out.The test results show that the improved structure can effectively improve the voltage resistance and robustness of ESD protective devices.The circuit of DC-DC converter is studied and designed. According to the voltage mode, the voltage conversion from 3.3 V to 1.2 V is realized by pulse width modulation. The working frequency is 1 MHz.The whole loop mainly includes main circuit, error amplifier, sawtooth wave generator, comparator, dead-time control and drive circuit, level conversion circuit, current detection circuit, logic control circuit.The current detection module and logic control circuit are added to the control loop to improve the problem of greatly reducing the conversion efficiency of the DC-DC converter in the load ER.By splitting the transistor and adjusting it automatically, the number of transistors working under small load current is reduced, thus the power consumption is reduced and the efficiency is improved.Four groups of simulation results show that the efficiency can be increased to more than 850% by using split transistor in the wide load range of 20-500mA.
【學(xué)位授予單位】：中國科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TM46

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