發(fā)布時間：2018-02-20 01:21

  本文關鍵詞： 鎖相環(huán) 相序解耦控制器 二階廣義積分器 諧波抑制　出處：《電力系統(tǒng)自動化》2017年16期 　論文類型：期刊論文

【摘要】：傳統(tǒng)鎖相環(huán)技術在三相電網電壓含有直流分量、發(fā)生不對稱故障以及嚴重畸變條件下,其檢測精度受到直流分量、負序分量及諧波分量的干擾,將不能準確跟蹤電網電壓頻率和相位。針對這一問題,提出一種將相序解耦諧振(SDR)控制器和改進的級聯雙二階廣義積分器軟件鎖相環(huán)(CDSOGI-SPLL)相結合的鎖相方法。該方法首先利用SDR控制器將正負序分量進行分離,然后引入改進的級聯雙二階廣義積分器(CDSOGI)對正負序分量進行二次分離和諧波抑制,并消除直流分量對CDSOGI輸出正交信號的影響。仿真和實驗結果表明,在三相電網電壓含有直流分量、不平衡和嚴重畸變情況下,所述方法可以實現電網電壓同步信息的準確采集。
[Abstract]:Under the condition that the voltage of three-phase power system contains DC component, the asymmetry fault and the serious distortion, the detection accuracy of the traditional PLL technique is disturbed by DC component, negative sequence component and harmonic component. Will not be able to accurately track the voltage frequency and phase of the grid. A phase locking method combining the phase sequence decoupling resonance (SDR) controller and the improved cascade double second order generalized integrator software phase locked loop (CDSOGI-SPLL) is proposed. The SDR controller is used to separate the positive and negative sequence components. Then an improved cascade double second order generalized integrator (CDSOGI) is introduced to carry out the secondary separation and harmonic suppression of the positive and negative sequence components, and to eliminate the influence of DC component on the output orthogonal signals of CDSOGI. The simulation and experimental results show that, Under the condition of DC component, unbalance and serious distortion of three-phase network voltage, the method can accurately collect the synchronous information of power grid voltage.
【作者單位】： 哈爾濱工業(yè)大學電氣工程及自動化學院;大連理工大學電氣工程學院;
【基金】：國家自然科學基金資助項目(51377013);國家自然科學基金青年基金資助項目(51407023)~~
【分類號】：TM761.12
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本文編號：1518429