隨著無線網(wǎng)絡(luò)傳感器應(yīng)用領(lǐng)域?qū)o線連接的要求不斷增長,物聯(lián)網(wǎng)和射頻識別方面都將研究力量集中在提出低成本、低功耗和更小型化的SOC設(shè)計方案上。由于CMOS技術(shù)在低成本和高集成度方面具有其獨特的優(yōu)勢,因此大多數(shù)收發(fā)機(jī)模塊在不影響性能的條件下都采用此技術(shù)設(shè)計。因為LNA是接收機(jī)端的第一個模塊,整個接收機(jī)的靈敏度和噪聲都取決于LNA的性能好壞。因此,根據(jù)ZigBee、IEEE802.11xx、BLE和RFID等不同應(yīng)用標(biāo)準(zhǔn)設(shè)計LNA將變得更具有挑戰(zhàn)性。基于不同的無線應(yīng)用標(biāo)準(zhǔn),本論文主要對實現(xiàn)集成多重增益、低噪聲、差分結(jié)構(gòu)、高IIP3線性和低功耗的低噪聲放大器進(jìn)行研究,設(shè)計了工作于3-3.04GHz的CMOS低噪聲放大器。所設(shè)計的LNA是基于CMOS GF-130nm工藝的,由輸入匹配、多核心放大器、輸出匹配和差分結(jié)構(gòu)組成。高頻情況下,LNA的靈敏度和功耗通常嚴(yán)格地取決于輸入匹配。當(dāng)它接收的信號從弱輸入射頻信號變化到更高的時候會消耗更多功率。針對這個問題,本文提出了一種多重共源共柵技術(shù)以實現(xiàn)不同的增益模式,且不影響輸入輸出匹配性能。為了實現(xiàn)較低的低噪聲設(shè)計,本文提出采用高Q值中心抽頭電感來實現(xiàn)低噪... 

【文章頁數(shù)】：87 頁

【學(xué)位級別】：碩士

【文章目錄】：
摘要
Abstract
Chapter 1 Introduction
    1.1 Overview
    1.2 Receiver Architecture
    1.3 3-GHz Transceiver
    1.4 Previous Work
    1.5 Scope & Organization of Thesis
Chapter 2 Matching Networks
    2.1 Introduction
    2.2 Matching Networks
        2.2.1 RLC Parallel Matching Network
        2.2.2 RLC Series Matching Network
        2.2.3 Q-Factor
        2.2.4 Maximum Power Transformation
        2.2.5 L-match Topology
        2.2.6 π-match Topology
        2.2.7 T-match Topology
    2.3 Summary
Chapter 3 Two-Port Network, Bandwidth & Noise
    3.1 Introduction
    3.2 Two-Port Network
        3.2.1 Y-Parameters
        3.2.2 S-Parameters
        3.2.3 Smith Chart
    3.3 Bandwidth Estimation
    3.4 Noise
        3.4.1 Thermal Noise
        3.4.2 Shot Noise
        3.4.3 Flicker Noise
    3.5 Summary
Chapter 4 LNA Design Constraints
    4.1 Introduction
    4.2 Noise Considerations
        4.2.1 Noise Figure
        4.2.2 Noise Temperature
    4.3 Network Gain
        4.3.1 Power Gain
        4.3.2 Transducer Gain
        4.3.3 Available Gain
    4.4 Linearity
        4.4.1 1-dB Compression Point (P1dB)
        4.4.2 Third Order Intercept Point (IP3)
    4.5 Summary
Chapter 5 Schematic & Layout Design
    5.1 Introduction
    5.2 Basic Topologies
        5.2.1 LNA with Input Shunt Resistor
        5.2.2 Common Gate LNA (CG)
        5.2.3 Resistive Feedback LNA
        5.2.4 Common Source LNA with Inductive Degeneration (CS)
        5.2.5 Comparison of Different Topologies
        5.2.6 Comparison of Different Design and Optimization Principles
    5.3 Schematic Design
        5.3.1 Input Matching
        5.3.2 Multigain Cascode Structure
        5.3.3 Differential Structure
        5.3.4 Inductive Source Degeneration
        5.3.5 Output Matching
        5.3.6 Biasing Structure
        5.3.7 Full Schematic Diagram
    5.4 Layout Design
    5.5 Post Simulation Results
    5.6 Summary
Chapter 6 Conclusion & Future Work
    6.1 Conclusion
    6.2 Future Work
    6.3 Summary
References
Acknowledgement
List of Publications



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