本文選題：萬兆以太網(wǎng) + XAUI接口�。� 參考：《大連理工大學(xué)》2014年碩士論文

【摘要】：視頻技術(shù)的飛速發(fā)展,高分辨率、高幀率圖像采集在科學(xué)研究和工業(yè)生產(chǎn)等領(lǐng)域中發(fā)揮著越來越重要的作用,而連續(xù)的高分辨率、高幀率圖像采集會(huì)產(chǎn)生巨大的數(shù)據(jù)量,因此必須采用具有更高信道容量的通信系統(tǒng)作為傳輸媒介,才能夠?qū)崿F(xiàn)高速數(shù)據(jù)圖像的可靠傳輸。 基于萬兆以太網(wǎng)標(biāo)準(zhǔn)IEEE802.3ae和FPGA技術(shù),設(shè)計(jì)了傳輸帶寬為lOGbps的嵌入式圖像系統(tǒng)。系統(tǒng)由應(yīng)用層邏輯模塊、數(shù)據(jù)鏈路層模塊和高速串行接口模塊三部分組成,其中應(yīng)用層邏輯模塊負(fù)責(zé)高速傳感器的配置和數(shù)據(jù)收發(fā)功能；數(shù)據(jù)鏈路層模塊負(fù)責(zé)以太網(wǎng)數(shù)據(jù)的編解碼以及幀校驗(yàn)功能；高速串行接口模塊負(fù)責(zé)將并行數(shù)據(jù)流轉(zhuǎn)化為高速串行數(shù)據(jù)流,實(shí)現(xiàn)與上位機(jī)的通信。 硬件設(shè)計(jì)方面,采用Xilinx公司的型號為Virtex-5LX50T的FPGA作為萬兆以太網(wǎng)傳輸卡的主控芯片,利用FPGA中的IP核實(shí)現(xiàn)收發(fā)萬兆以太網(wǎng)數(shù)據(jù)協(xié)議,利用XAUI核和內(nèi)置的GTP高速收發(fā)器硬核實(shí)現(xiàn)高速串行數(shù)據(jù)的傳輸；萬兆以太網(wǎng)物理層使用Broadcom公司的專用芯片BCM8706,用于實(shí)現(xiàn)XAUI接口數(shù)據(jù)到XFI接口數(shù)據(jù)的相互轉(zhuǎn)換。BCM8706芯片采用10GBASE-LRM串行傳輸標(biāo)準(zhǔn),實(shí)現(xiàn)220m的傳輸距離。光收發(fā)器采用Finisar公司的SFP+接口光模塊,實(shí)現(xiàn)10.3125Gbps光電信號轉(zhuǎn)換和傳輸。 系統(tǒng)軟件方面設(shè)計(jì)主要為FPGA中的邏輯設(shè)計(jì)和應(yīng)用程序設(shè)計(jì)。使用VerilogHDL語言完成FPGA邏輯設(shè)計(jì),實(shí)現(xiàn)CMOS傳感器的配置以及各個(gè)模塊之間的驅(qū)動(dòng)時(shí)序和控制信號；在FPGA中開辟兩塊雙口RAM緩存數(shù)據(jù),根據(jù)圖像傳感器的數(shù)據(jù)傳輸特點(diǎn)設(shè)計(jì)了乒乓讀寫時(shí)序,解決海量數(shù)據(jù)的直傳問題。基于開源的編程接口WinPcap和MFC設(shè)計(jì)了網(wǎng)絡(luò)數(shù)據(jù)包獲取與恢復(fù)應(yīng)用程序,使用C++語言編程,實(shí)現(xiàn)網(wǎng)絡(luò)數(shù)據(jù)的直接存儲(chǔ)以及圖像的回放功能。 在論文最后給出系統(tǒng)調(diào)試流程及性能分析,經(jīng)過測試傳輸卡可以實(shí)現(xiàn)10Gbps的數(shù)據(jù)傳輸,應(yīng)用程序可以實(shí)現(xiàn)穩(wěn)定的圖像存儲(chǔ)與回放功能。
[Abstract]:With the rapid development of video technology, high resolution and high frame rate image acquisition is playing a more and more important role in the fields of scientific research and industrial production, while continuous high resolution and high frame rate image acquisition will produce a huge amount of data. Therefore, the communication system with higher channel capacity must be used as the transmission medium in order to realize the reliable transmission of high-speed data images. Based on the standard IEEE802.3ae and FPGA technology of Gigabit Ethernet, an embedded image system with transmission bandwidth of lOGbps is designed. The system consists of three parts: application layer logic module, data link layer module and high speed serial interface module. The application layer logic module is responsible for the configuration of high speed sensor and the function of data receiving and sending. The data link layer module is responsible for the Ethernet data coding and decoding and the frame checking function, and the high-speed serial interface module is responsible for converting the parallel data stream into the high speed serial data stream to realize the communication with the host computer. In the aspect of hardware design, the FPGA of Virtex-5LX50T of Xilinx Company is used as the main control chip of Gigabit Ethernet transmission card, and the IP core of FPGA is used to realize the data protocol of sending and receiving Gigabit Ethernet. The XAUI core and the hard core of the GTP high-speed transceiver are used to realize the high speed serial data transmission. The physical layer of Gigabit Ethernet uses BCM8706, a special chip of Broadcom Company, to realize the conversion between XAUI interface data and XFI interface data. BCM8706 chip adopts 10GBASE-LRM serial transmission standard and realizes the transmission distance of 220m. The optical transceiver uses Finisar SFP interface optical module to realize 10.3125Gbps photoelectric signal conversion and transmission. The design of system software is mainly logic design and application program design in FPGA. VerilogHDL language is used to complete FPGA logic design, to realize the configuration of CMOS sensor, drive timing and control signal between modules, and to open two blocks of double-port RAM to cache data in FPGA. According to the data transmission characteristics of image sensor, a ping-pong reading and writing time sequence is designed to solve the problem of direct transmission of mass data. The application program of network packet acquisition and recovery is designed based on open source programming interfaces WinPcap and MFC. C language is used to program to realize the direct storage of network data and the function of image playback. At the end of the paper, the system debugging flow and performance analysis are given. After testing the transmission card, the 10Gbps data transmission can be realized, and the application program can realize the stable image storage and playback function.
【學(xué)位授予單位】：大連理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TP393.11

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