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基于通用多核平臺的高速網(wǎng)絡處理系統(tǒng)關鍵技術研究

發(fā)布時間:2018-05-07 19:53

  本文選題:通用多核處理器 + 高性能網(wǎng)絡處理程序; 參考:《中國科學技術大學》2014年博士論文


【摘要】:隨著萬兆鏈路進入實際部署以及數(shù)據(jù)包處理功能迅速向協(xié)議棧高層轉移,網(wǎng)絡系統(tǒng)的處理能力正面臨越來越嚴峻的挑戰(zhàn)。傳統(tǒng)上,高速網(wǎng)絡設備主要依靠專用硬件(如ASIC、網(wǎng)絡處理器)達到高性能。但是硬件方案可編程性差,只能承擔簡單的包處理功能。隨著網(wǎng)絡應用日趨復雜,網(wǎng)絡系統(tǒng)的處理任務正從簡單的包轉發(fā)、包過濾演變到深度數(shù)據(jù)包檢查、網(wǎng)絡異常檢測、基于內(nèi)容的交換、數(shù)據(jù)加密等復雜功能。這種深度的包處理要求網(wǎng)絡系統(tǒng)提供更多的計算能力和編程靈活性。 自雙核處理器出現(xiàn)后,通用多核處理器的發(fā)展令人矚目。目前通用多核處理器的核數(shù)已經(jīng)接近、甚至超過了網(wǎng)絡處理器中計算單元的數(shù)量,其高層協(xié)議處理能力更是專用硬件無法比擬的。基于通用多核平臺開發(fā)網(wǎng)絡設備已成為目前學術界和工業(yè)界感興趣的研究課題。然而通用多核平臺并不是為網(wǎng)絡處理而設計,將它應用于高速網(wǎng)絡系統(tǒng)面臨諸多難題,比如缺乏高效的核間通信機制,通用操作系統(tǒng)的網(wǎng)絡子系統(tǒng)不夠高效,網(wǎng)絡程序的并行化方法沒有先例可借鑒,等等。 本論文系統(tǒng)研究基于通用多核平臺構建高速網(wǎng)絡系統(tǒng)的若干關鍵技術,并在Intel通用多核平臺和Linux操作系統(tǒng)上實現(xiàn)網(wǎng)絡系統(tǒng)原型。本論文從構建一個具體的網(wǎng)絡流量監(jiān)視系統(tǒng)入手,研究并實現(xiàn)流水線并行模型、高效的核間通信機制、基于無鎖設計的全局數(shù)據(jù)結構、串行代碼到并行代碼的轉換等關鍵技術。 本論文的主要貢獻及創(chuàng)新點如下: (1)結合流水線并行和任務級并行模型,在Intel通用多核平臺上實現(xiàn)了一個高性能的流量監(jiān)視系統(tǒng)原型。該系統(tǒng)原型可達到2Gbps應用層處理能力。 (2)針對流水線并行模型中最關鍵的流水線級間通信問題,設計并實現(xiàn)了一個簡單、高效且實用的單生產(chǎn)者/單消費者并發(fā)無鎖隊列B-Queue。B-Queue性能與已有同類算法相同,且在真實環(huán)境中性能穩(wěn)定。 (3)針對全局數(shù)據(jù)結構共享難有有效解決方案的問題,提出面向特定應用設計定制化無鎖數(shù)據(jù)結構的解決思路和方法,并運用到一個具體的TCP SYN洪泛攻擊檢測應用程序中,為將無鎖設計思想運用到具體的程序設計實踐中進行了有益的探索。 本論文工作為利用通用多核服務器建立高速網(wǎng)絡系統(tǒng)的研究與實踐積累了寶貴的經(jīng)驗。
[Abstract]:With the actual deployment of the multi-megabit link and the rapid transfer of the packet processing function to the high layer of the protocol stack, the processing capability of the network system is facing more and more severe challenges. Traditionally, high-speed network devices mainly rely on dedicated hardware (such as ASIC, network processor) to achieve high performance. However, the hardware program is not programmable, and can only undertake simple packet processing functions. With the increasing complexity of network applications, the processing tasks of network systems are changing from simple packet forwarding, packet filtering to deep packet checking, network anomaly detection, content-based exchange, data encryption and other complex functions. This depth of packet processing requires more computing power and programming flexibility for network systems. Since the emergence of dual-core processors, the development of universal multi-core processors has attracted much attention. At present, the number of cores of general multi-core processors is close to, even more than the number of computing units in network processors, and its high-level protocol processing capability is incomparable to that of dedicated hardware. Developing network equipment based on general multi-core platform has become an interesting research topic in academia and industry. However, the general multi-core platform is not designed for network processing. The application of the platform to high-speed network systems faces many difficulties, such as the lack of efficient inter-core communication mechanism, the lack of efficient network subsystem of the general operating system. There is no precedent for parallelization of network programs, and so on. In this paper, some key technologies of constructing high speed network system based on general multi-core platform are studied, and the prototype of network system is implemented on Intel platform and Linux operating system. Starting with the construction of a specific network traffic monitoring system, this paper studies and implements pipeline parallel model, efficient inter-core communication mechanism, global data structure based on lock-free design, and the conversion from serial code to parallel code. The main contributions and innovations of this thesis are as follows: 1) combining pipelined parallelism and task-level parallelism, a high-performance traffic monitoring system prototype is implemented on Intel universal multi-core platform. The prototype of the system can achieve 2Gbps application layer processing capability. In order to solve the most critical problem of pipeline level communication in pipeline parallel model, a simple, efficient and practical single producer / consumer concurrent lock-free queue B-Queue.B-Queue is designed and implemented, which has the same performance as existing algorithms. And the performance is stable in the real environment. In order to solve the problem that it is difficult to share global data structure effectively, this paper puts forward the solution of customizing lock free data structure for specific applications, and applies it to a concrete TCP SYN flood attack detection application program. In order to apply the lock-free design thought to the concrete programming practice, this paper makes a beneficial exploration. This thesis has accumulated valuable experience for the research and practice of establishing high-speed network system using universal multi-core server.
【學位授予單位】:中國科學技術大學
【學位級別】:博士
【學位授予年份】:2014
【分類號】:TP393.05

【共引文獻】

相關期刊論文 前1條

1 杜延寧;趙銀亮;韓博;李遠成;;一種數(shù)據(jù)結構制導的線程劃分方法與執(zhí)行模型[J];軟件學報;2013年10期

相關博士學位論文 前1條

1 李彬;自動交換光網(wǎng)絡中的預配置環(huán)保護技術研究[D];北京郵電大學;2010年

相關碩士學位論文 前10條

1 楊朝輝;主存數(shù)據(jù)庫索引機制的研究與改進[D];南京航空航天大學;2011年

2 張耀政;基于FPGA實時處理的視頻圖像增強技術[D];中北大學;2010年

3 廖泉清;高性能入侵檢測系統(tǒng)的優(yōu)化設計與實現(xiàn)[D];中南大學;2012年

4 周勇勃;AFDX網(wǎng)絡MAC功能模塊的設計與驗證[D];西安電子科技大學;2013年

5 劉恒;并發(fā)數(shù)據(jù)結構及其在動態(tài)內(nèi)存管理中的應用[D];重慶大學;2013年

6 石彥博;網(wǎng)絡硬盤系統(tǒng)中的數(shù)據(jù)私密性與一致性技術研究[D];遼寧師范大學;2013年

7 孟偉;企業(yè)即時通訊系統(tǒng)服務器的設計與實現(xiàn)[D];浙江工業(yè)大學;2013年

8 譚龍飛;基于副本的非阻塞自組織鏈表[D];天津大學;2012年

9 趙麗偉;基于虛擬儀器技術的萬能試驗機測控系統(tǒng)研究[D];天津科技大學;2012年

10 趙立飛;基于TL2軟件事務內(nèi)存機制的并發(fā)程序的精化驗證[D];中國科學技術大學;2014年



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