本文選題：高性能計(jì)算　切入點(diǎn)：高階路由器　出處：《計(jì)算機(jī)工程與科學(xué)》2017年02期

【摘要】：隨著高性能網(wǎng)絡(luò)規(guī)模的增加,高階路由器結(jié)構(gòu)設(shè)計(jì)成為高性能計(jì)算研究的重點(diǎn)和熱點(diǎn)。使用高階路由器,網(wǎng)絡(luò)能實(shí)現(xiàn)更低的報(bào)文傳輸延遲、網(wǎng)絡(luò)功耗和網(wǎng)絡(luò)構(gòu)建成本,同時(shí)高階路由器的應(yīng)用還可以提高網(wǎng)絡(luò)可靠性。高性能路由器的階數(shù)不斷提高,僅靠擴(kuò)展單級(jí)crossbar交換結(jié)構(gòu)的階數(shù)使路由器內(nèi)部的連線資源急速增長(zhǎng),交叉開(kāi)關(guān)的實(shí)現(xiàn)代價(jià)將不可接受,這就需要為高階路由器設(shè)計(jì)新型的交換結(jié)構(gòu)。近十年來(lái),出現(xiàn)了以YARC為代表的經(jīng)典結(jié)構(gòu)化設(shè)計(jì)以及"network within a network"等新型設(shè)計(jì)方法,未來(lái)的研究重點(diǎn)是解決高階路由器結(jié)構(gòu)設(shè)計(jì)中遇到的緩存、仲裁和擴(kuò)展性等各種問(wèn)題。鑒于此,實(shí)現(xiàn)了一種多級(jí)無(wú)緩存高階路由器,這種高階路由器內(nèi)部是一個(gè)多級(jí)Clos網(wǎng)絡(luò),每一級(jí)有相應(yīng)的仲裁模塊對(duì)請(qǐng)求進(jìn)行調(diào)度,數(shù)據(jù)包緩存在輸入/輸出端口實(shí)現(xiàn),除去這些緩沖區(qū)單元,該網(wǎng)絡(luò)是無(wú)緩存的。最后通過(guò)BookSim模擬器進(jìn)行了大量的性能測(cè)試,所設(shè)計(jì)的路由器能夠正常工作,性能良好。
[Abstract]:With the increase of the scale of high performance network, the structure design of high-order router becomes the focus and hotspot of high-performance computing.Using high-order routers, the network can achieve lower packet transmission delay, network power consumption and network construction cost, and the application of high-order routers can also improve network reliability.The order of high performance router is increasing continuously. Only by extending the order of single-stage crossbar switch structure, the connection resource inside router increases rapidly, and the cost of implementing crossover switch will be unacceptable.This requires the design of a new switching architecture for higher-order routers.In recent ten years, classical structured design, represented by YARC, and new design methods such as "network within a network" have emerged. In the future, the focus of research is to solve the problems of cache, arbitration and expansibility encountered in the structural design of high-order routers.In view of this, a multi-level cache free high-order router is implemented. This kind of high-order router is a multi-level Clos network, each level has a corresponding arbitration module to schedule the request, and the data packet cache is implemented in the input / output port.Without these buffer units, the network is cache-free.Finally, a large number of performance tests are carried out through the BookSim simulator, and the designed router can work normally and has good performance.
【作者單位】： 國(guó)防科學(xué)技術(shù)大學(xué)計(jì)算機(jī)學(xué)院;
【基金】：國(guó)家自然科學(xué)基金(61272482) 全國(guó)百篇優(yōu)秀博士論文基金(201450) 國(guó)家863計(jì)劃(2015AA01A301)
【分類號(hào)】：TP393.05

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