本文關(guān)鍵詞： 射頻識別技術(shù) 鎖相環(huán) 壓控振蕩器 電荷泵 分頻器　出處：《中國科學(xué)技術(shù)大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：射頻識別技術(shù)具有信息量大、無需接觸即可快速識別大量物品的優(yōu)點,可以極大提高物流鏈管理中物品信息的時效及準確度,逐漸成為學(xué)術(shù)及工業(yè)界的研究熱點。另一方面,隨著CMOS技術(shù)發(fā)展進入納米時代,高度集成的片上系統(tǒng)成為了電路設(shè)計的主流方向,帶給射頻識別閱讀器芯片巨大的研究及應(yīng)用潛力。 頻率綜合器為閱讀器芯片提供本振信號,是決定閱讀器芯片收發(fā)性能的關(guān)鍵部分,其設(shè)計難點在于壓控振蕩器和電荷泵電路的設(shè)計。本文以設(shè)計一款適用于中國大陸標(biāo)準的射頻識別閱讀器芯片中的頻率綜合器為目標(biāo),提出采用雙環(huán)整數(shù)型鎖相環(huán)架構(gòu),并在詳細分析環(huán)路各電路模塊的設(shè)計方法及參數(shù)選取原則下,采用3.3V/1.8V130nm CMOS工藝實現(xiàn)并通過流片測試或后仿驗證。 高性能壓控振蕩器的是鎖相環(huán)設(shè)計的基礎(chǔ),直接決定環(huán)路的帶外噪聲和功耗。目前主流的兩種CMOS壓控振蕩器為環(huán)形振蕩器和電感電容振蕩器,本文試圖以最小的功耗實現(xiàn)壓控振蕩器的最優(yōu)噪聲性能。在分析環(huán)振差分延時單元熱噪聲傳遞的基礎(chǔ)上,明確給出并流片驗證了延時單元中MOS管尺寸及負載類型的選取和設(shè)計原則,降低環(huán)振相位噪聲。從電感選取、變?nèi)莨芷脙?yōu)化、電容陣列、交叉耦合管及偏置電流源管選擇五個方面,提出并后仿驗證了低相位噪聲電感電容振蕩器的優(yōu)化方法。 電荷泵的性能好壞影響鎖相環(huán)路的帶內(nèi)噪聲及參考雜散水平,低功耗低參考雜散是電荷泵電路設(shè)計的優(yōu)化方向。本文分析了影響電荷泵參考雜散和噪聲的非理想效應(yīng),給出了對應(yīng)的數(shù)學(xué)模型,并據(jù)此設(shè)計了一個輸出參考雜散在-88dBc以下,5位開關(guān)控制尾電流大小的電荷泵電路。 最后,本文還實現(xiàn)了鎖相環(huán)路中的數(shù)字電路模塊的設(shè)計,主要指鑒頻鑒相器和分頻器部分。根據(jù)鎖相環(huán)路中各處不同的信號工作頻率,給出了鎖相環(huán)中用到的三處分頻器的設(shè)計方案及后仿結(jié)果。
[Abstract]:RFID technology has the advantages of large amount of information, can quickly identify a large number of items without contact, and can greatly improve the timeliness and accuracy of goods information in logistics chain management. On the other hand, with the development of CMOS technology into the nanoscale era, the highly integrated on-chip system has become the mainstream of circuit design. It brings enormous research and application potential to RFID reader chip. The frequency synthesizer provides the local oscillator signal for the reader chip, which is the key part of determining the transceiver performance of the reader chip. The design difficulty lies in the design of voltage controlled oscillator and charge pump circuit. This paper aims to design a frequency synthesizer in RFID reader chip suitable for Chinese mainland standard. A dual loop integer PLL architecture is proposed, and the design method and parameter selection principle of each circuit module of the loop are analyzed in detail. A 3.3V / 1.8V130nm CMOS process was used and the flow sheet test or post-simulation verification was carried out. The high performance VCO is the basis of PLL design, which directly determines the out-of-band noise and power consumption of the loop. At present, two kinds of CMOS VCO are ring oscillator and inductively capacitive oscillator. This paper attempts to achieve the optimal noise performance of the VCO with minimum power consumption, based on the analysis of the thermal noise transfer of the ring vibration differential delay unit. The principle of selecting and designing the size and load type of MOS tube in delay cell is clearly given. The phase noise of ring vibration is reduced from inductance selection, transformer bias optimization, capacitor array. The optimization method of low phase noise inductively capacitive oscillator is proposed and verified in the selection of cross-coupled transistors and bias current source transistors. The performance of the charge pump affects the in-band noise and the reference stray level of the PLL. Low power and low reference stray is the optimization direction of charge pump circuit design. This paper analyzes the non-ideal effects of the charge pump reference stray and noise, and gives the corresponding mathematical model. Based on this, a charge pump circuit with output reference stray below -88dBc is designed. Finally, the design of the digital circuit module in the PLL is realized, which mainly refers to the frequency discriminator and the frequency divider. According to the different signal operating frequency in the PLL. The design scheme and post-simulation results of three frequency dividers used in PLL are given.
【學(xué)位授予單位】：中國科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN74;TP391.44

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本文編號：1441830