本文選題：高頻 + 射頻識別��； 參考：《華中科技大學(xué)》2014年碩士論文

【摘要】：近年來，射頻識別（Radio Frequency Identification-RFID）技術(shù)在供應(yīng)鏈管理、公共交通、零售業(yè)、物流跟蹤和門禁系統(tǒng)等領(lǐng)域中有著廣泛的應(yīng)用。隨著物聯(lián)網(wǎng)技術(shù)和無線傳感網(wǎng)絡(luò)技術(shù)的發(fā)展，集成傳感器的RFID標(biāo)簽芯片成為了RFID技術(shù)發(fā)展趨勢。半有源標(biāo)簽由于自身攜帶電池，突破了功耗瓶頸，為傳感器、高強度的安全算法等功能在射頻系統(tǒng)中的應(yīng)用提供了可能。因此，半有源標(biāo)簽在RFID標(biāo)簽芯片功能性增強的趨勢下有著巨大的應(yīng)用前景。本文針對高頻半有源RFID標(biāo)簽芯片模擬前端系統(tǒng)和關(guān)鍵模塊進行了研究和實現(xiàn)。 首先，本文闡述了半有源標(biāo)簽芯片工作原理，并從識讀距離和使用壽命兩個方面分析了半有源標(biāo)簽芯片的關(guān)鍵性能，同時構(gòu)建了高頻半有源標(biāo)簽芯片模擬前端的系統(tǒng)架構(gòu)。 其次，本文對高頻半有源RFID標(biāo)簽芯片模擬前端的關(guān)鍵模塊進行了研究和設(shè)計，其中闡明了NMOS柵交叉全波整流電路的輸出電壓與其損耗來源，介紹并分析了目前常用的時序檢測喚醒電路和能量檢測喚醒電路，在解調(diào)理論分析的基礎(chǔ)上構(gòu)建了適用于高頻半有源RFID標(biāo)簽芯片的10%ASK解調(diào)和100%解調(diào)電路，，同時研究了低成本的副載波返回調(diào)制的機理和實現(xiàn)方式。 最后，本文基于華虹NEC0.13μm1P4M CMOS工藝優(yōu)化并實現(xiàn)了適用于ISO/IEC14443Type A協(xié)議的高頻半有源RFID標(biāo)簽芯片的模擬前端電路。仿真結(jié)果顯示，該模擬前端實現(xiàn)了喚醒電路約100pW的極低休眠功耗和相對于無源模擬前端更遠的識讀距離，更大的帶載能力。該模擬前端芯片面積為416μm×472μm，投片后芯片與基于FPGA的數(shù)字基帶進行測試，采用ASK100%調(diào)制方式，能與讀寫器進行正常通信，標(biāo)簽返回讀寫器信號調(diào)制深度達16.4%，大大高于讀寫器識別要求。測試表明該模擬前端可應(yīng)用于高頻半有源RFID標(biāo)簽整體芯片中。
[Abstract]:In recent years, Radio Frequency Identification-RFIDation-RFID technology has been widely used in supply chain management, public transport, retail, logistics tracking and access control systems. With the development of Internet of things (IoT) and wireless sensor network (WSN) technology, RFID tag chip integrated with sensor has become the trend of RFID technology. The semi-active tag has broken through the bottleneck of power consumption because of carrying battery itself, which provides the possibility for the application of sensor, high-intensity security algorithm and other functions in RF system. Therefore, semi-active tag has a great application prospect in the trend of RFID tag chip functionality enhancement. In this paper, the analog front end system and key modules of high frequency semi-active RFID tag chip are studied and implemented. Firstly, this paper describes the working principle of semi-active tag chip, and analyzes the key performance of semi-active tag chip from the aspects of reading distance and service life. At the same time, the system architecture of high-frequency semi-active tag chip analog front-end is constructed. Secondly, this paper studies and designs the key modules of the analog front-end of the high-frequency semi-active RFID tag chip, in which the output voltage and the loss source of the NMOS gate cross-full-wave rectifier circuit are clarified. This paper introduces and analyzes the current time sequence detection wake-up circuit and energy detection wake-up circuit. Based on the analysis of demodulation theory, the 10%ASK demodulation circuit and 100% demodulation circuit suitable for high frequency semi-active RFID tag chip are constructed. At the same time, the mechanism and implementation of low cost subcarrier return modulation are studied. Finally, based on Huahong NEC0.13 渭 m1P4M CMOS technology, the analog front-end circuit of high-frequency semi-active RFID tag chip suitable for ISO/IEC14443Type A protocol is optimized and implemented. The simulation results show that the analog front-end realizes the very low dormant power consumption of the arousal circuit about 100pW, the longer reading distance and the larger load capacity compared with the passive analog front-end. The area of the analog front-end chip is 416 渭 m 脳 472 渭 m. The chip is tested with the digital baseband based on FPGA. The ASK100% modulation mode can communicate with the reader normally, and the modulation depth of the label return reader signal reaches 16.4g, which is much higher than the recognition requirement of the reader. The test shows that the analog front end can be used in the whole chip of high frequency semi-active RFID tag.
【學(xué)位授予單位】：華中科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TP391.44

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本文編號：1924882