矢量陣目標(biāo)探測(cè)系統(tǒng)信號(hào)預(yù)處理分機(jī)的設(shè)計(jì)
發(fā)布時(shí)間:2018-11-21 21:20
【摘要】:隨著人們對(duì)海洋開(kāi)發(fā)投入的增加,基于矢量水聽(tīng)器陣列的目標(biāo)探測(cè)系統(tǒng)的研究受到了越來(lái)越多的重視。信號(hào)預(yù)處理分機(jī)作為目標(biāo)探測(cè)系統(tǒng)的重要組成部分,承擔(dān)著信號(hào)調(diào)理、采集、緩存以及數(shù)據(jù)傳輸?shù)戎匾ぷ鳌k[身及減振降噪技術(shù)的發(fā)展,對(duì)目標(biāo)探測(cè)系統(tǒng)的預(yù)處理分機(jī)提出了更高的要求。本文設(shè)計(jì)并實(shí)現(xiàn)了矢量陣目標(biāo)探測(cè)系統(tǒng)信號(hào)預(yù)處理分機(jī),主要采用FPGA及Nios Ⅱ處理器來(lái)完成全部工作。本論文完成了矢量陣目標(biāo)探測(cè)系統(tǒng)信號(hào)預(yù)處理分機(jī)硬件設(shè)計(jì)與軟件調(diào)試。首先,根據(jù)系統(tǒng)設(shè)計(jì)提出的需求,按照其功能與任務(wù)的差異,本文模塊化地對(duì)硬件進(jìn)行了設(shè)計(jì),包括芯片選型、電路原理圖的設(shè)計(jì),PCB的設(shè)計(jì)。硬件主要包括信號(hào)調(diào)理電路、網(wǎng)絡(luò)供電電路、數(shù)據(jù)采集電路和以太網(wǎng)接口電路。其次,在FPGA平臺(tái)上搭載了以Nios Ⅱ及外圍接口為核心的片上系統(tǒng),實(shí)現(xiàn)了TSE_MAC+PHY架構(gòu)的網(wǎng)絡(luò)數(shù)據(jù)傳輸模塊,基于Avalon總線規(guī)范添加了自定義FIFO與RAM,對(duì)電源電路、AD采集時(shí)序、數(shù)據(jù)緩存時(shí)序以及以太網(wǎng)接口模塊進(jìn)行了調(diào)試隨后,編寫(xiě)了數(shù)據(jù)緩存的管理邏輯與以太網(wǎng)數(shù)據(jù)傳輸?shù)某绦颉1驹O(shè)計(jì)通過(guò)FPGA實(shí)現(xiàn)AD芯片的控制邏輯,對(duì)13路信號(hào)進(jìn)行實(shí)時(shí)采樣與緩存,利用Nios Ⅱ處理器對(duì)緩存的數(shù)據(jù)進(jìn)行傳輸,最終傳輸至上位機(jī)的硬盤,以文件的形式保存。最后,本文對(duì)預(yù)處理平臺(tái)進(jìn)行了測(cè)試與驗(yàn)證,包括AD采樣的測(cè)試,數(shù)據(jù)接收存儲(chǔ)的測(cè)試、以太網(wǎng)的聯(lián)合測(cè)試、羅經(jīng)數(shù)據(jù)傳輸?shù)臏y(cè)試和湖上實(shí)驗(yàn)。在文章的結(jié)尾,總結(jié)設(shè)計(jì)的經(jīng)驗(yàn)與不足,明確了改進(jìn)的方向,為更好地發(fā)揮矢量陣目標(biāo)探測(cè)系統(tǒng)的效能做出準(zhǔn)備。
[Abstract]:With the increasing investment in ocean development, more and more attention has been paid to the research of target detection system based on vector hydrophone array. As an important part of the target detection system, the signal preprocessing extension is responsible for signal conditioning, acquisition, buffer and data transmission. With the development of stealth and vibration reduction and noise reduction technology, the preprocessing extension of target detection system is required higher. In this paper, the signal preprocessing extension of vector array target detection system is designed and implemented, which mainly uses FPGA and Nios 鈪,
本文編號(hào):2348282
[Abstract]:With the increasing investment in ocean development, more and more attention has been paid to the research of target detection system based on vector hydrophone array. As an important part of the target detection system, the signal preprocessing extension is responsible for signal conditioning, acquisition, buffer and data transmission. With the development of stealth and vibration reduction and noise reduction technology, the preprocessing extension of target detection system is required higher. In this paper, the signal preprocessing extension of vector array target detection system is designed and implemented, which mainly uses FPGA and Nios 鈪,
本文編號(hào):2348282
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