【摘要】：近年來，國內(nèi)橫機(jī)銷量猛增，，市場缺口巨大。各橫機(jī)生產(chǎn)廠商通過不斷創(chuàng)新，橫機(jī)控制技術(shù)不斷創(chuàng)新，功能更加齊全，穩(wěn)定性能更好，操作更加方便。本文結(jié)合橫機(jī)的發(fā)展趨勢，開發(fā)了一種基于總線結(jié)構(gòu)、擴(kuò)展性好的橫機(jī)硬件平臺。論文的主要研究內(nèi)容有： 研究了橫機(jī)的控制任務(wù)需求，設(shè)計了基于現(xiàn)場總線的三層分布式橫機(jī)控制系統(tǒng)總體結(jié)構(gòu)。分析了橫機(jī)控制系統(tǒng)通信實時性需求以及CAN總線通信技術(shù)的優(yōu)缺點(diǎn)，提出了采用自主知識產(chǎn)權(quán)的NCUC-Bus(NC Union of China Field Bus)作為主控制層和機(jī)頭控制層間的通信解決方案。 選取高性能的ARM芯片作為硬件平臺的控制核心，選用低功耗的外圍器件，并設(shè)計了相應(yīng)的接口電路。FPGA（Field-Programmable Gate Array）作為NCUC-Bus現(xiàn)場總線數(shù)據(jù)鏈路層的邏輯控制核心，集成裁剪后的通信協(xié)議，實現(xiàn)了可靠的數(shù)據(jù)傳輸。分析了機(jī)頭執(zhí)行元件的動作原理，設(shè)計了相應(yīng)的驅(qū)動電路。 分析了單機(jī)頭雙系統(tǒng)橫機(jī)機(jī)頭執(zhí)行數(shù)據(jù)的格式，依托所開發(fā)的硬件平臺，提出了分段式傳輸存儲的應(yīng)用層協(xié)議通信方案，保證了機(jī)頭通信的實時性。研究了橫機(jī)同步控制原理，設(shè)計了機(jī)頭位置計算、通信周期補(bǔ)償?shù)瓤刂颇K，實現(xiàn)了機(jī)頭執(zhí)行元件的同步控制。 搭建了實驗測試平臺，提出了基于FPGA的總線通信鏈路的調(diào)試方法，對通信鏈路的實時性及平臺的手動和自動模式等控制功能進(jìn)行了全面測試。開發(fā)的橫機(jī)控制平臺實現(xiàn)了橫機(jī)的控制，編織了標(biāo)準(zhǔn)樣件。達(dá)到了設(shè)計要求。
[Abstract]:In recent years, domestic flat machine sales soared, the market gap is huge. Through continuous innovation, flat machine control technology innovation, more complete function, more stable performance, more convenient operation. In this paper, a kind of hardware platform with good expansibility based on bus structure is developed according to the development trend of flat machine. The main contents of this paper are as follows: the control task requirement of the horizontal machine is studied, and the overall structure of the three-layer distributed control system based on the field bus is designed. This paper analyzes the real-time communication requirements of the flat machine control system and the advantages and disadvantages of the CAN bus communication technology, and puts forward a solution to the communication between the main control layer and the head control layer using the NCUC-Bus (NC Union of China Field Bus) with independent intellectual property rights. The high performance ARM chip is chosen as the control core of the hardware platform and the low power peripheral device is selected. The corresponding interface circuit. FPGA (Field-Programmable Gate Array) is designed as the logical control core of the NCUC-Bus fieldbus data link layer. Integration of the clipped communication protocol, the implementation of reliable data transmission. The operating principle of the head actuator is analyzed, and the corresponding driving circuit is designed. This paper analyzes the format of the execution data of single head and double system flat machine head, and based on the developed hardware platform, puts forward an application layer protocol communication scheme of segmented transmission and storage, which ensures the real time of the head communication. The synchronous control principle of the horizontal machine is studied and the control modules such as head position calculation and communication period compensation are designed to realize the synchronous control of the head executive element. The experimental test platform is built, and the debugging method of the bus communication link based on FPGA is proposed. The real-time performance of the communication link and the control functions of the platform such as manual and automatic mode are tested comprehensively. The flat machine control platform has realized the control of the flat machine and woven standard samples. Meet the design requirements.
【學(xué)位授予單位】：華中科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP273

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